Power Management - Xilinx KC705 User Manual

Chapter 1: KC705 Evaluation Board Features
Table 1-29: LPC Connections, J2 to FPGA U1 (Cont'd)
J2
Schematic Net Name
Pin
G33 FMC_LPC_LA31_P
G34 FMC_LPC_LA31_N
G36 FMC_LPC_LA33_P
G37 FMC_LPC_LA33_N
G39 VADJ

Power Management

[Figure
The KC705 board uses power regulators and PMBus compliant digital PWM system
controllers from Texas Instruments to supply core and auxiliary voltages. The Texas
Instruments Fusion Digital Power graphical user interface (GUI) is used to monitor the
current and temperature levels of the board power modules. If any module temperature
approaches 85°C then forced air cooling must be provided to keep the module temperature
within rated limits.
The PCB layout and power system have been designed to meet the recommended criteria
described in 7 Series FPGAs PCB Design and Pin Planning Guide (UG483)
64
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U1
J2
I/O Standard FPGA
Pin
Pin
LVDS AD29 H31
LVDS AE29 H32
LVDS AC29 H34
LVDS AC30 H35
H37
H38
H40
1-2, callout 32]
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Schematic Net Name
FMC_LPC_LA28_P
FMC_LPC_LA28_N
FMC_LPC_LA30_P
FMC_LPC_LA30_N
FMC_LPC_LA32_P
FMC_LPC_LA32_N
VADJ
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
U1
I/O Standard FPGA
Pin
LVDS AE30
LVDS AF30
LVDS AB29
LVDS AB30
LVDS Y30
LVDS AA30
[Ref 21].