Ethernet Phy Clock Source - Xilinx ZC702 User Manual

The Ethernet connections from the XC7Z020 AP SoC at U1 to the 88E1116R PHY device at
U35 are listed in
Table 1-14: Ethernet Connections, XC7Z020 AP SoC to the PHY Device
XC7Z020 (U1) Pin
Pin Name
PS_MIO53
PS_MIO52
PS_MIO16
PS_MIO21
PS_MIO20
PS_MIO19
PS_MIO18
PS_MIO17
PS_MIO22
PS_MIO27
PS_MIO26
PS_MIO25
PS_MIO24
PS_MIO23

Ethernet PHY Clock Source

[Figure 1-2, callout 10]
A 25.00 MHz 50 ppm crystal at X1 is the clock source for the 88E1116R PHY at U35.
Figure 1-14 shows the clock source.
X-Ref Target - Figure 1-14
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
Table 1-14.
Pin
Bank
Number
501 C12
501 D10
501 D6
501 F11
501 A8
501 E10
501 A7
501 E9
501 A14
501 D7
501 A13
501 F12
501 B7
501 E11
C322
18pF 50V
NPO
X1
25.00 MHz
3
R246
DNP
C333
2
18pF 50V
NPO
GND
Figure 1-14: Ethernet PHY Clock Source
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M88E1116R PHY U35
Schematic
Net Name
Pin
PHY_MDIO 45
PHY_MDC 48
PHY_TX_CLK 60
PHY_TX_CTRL 63
PHY_TXD3 62
PHY_TXD2 61
PHY_TXD1 59
PHY_TXD0 58
PHY_RX_CLK 53
PHY_RX_CTRL 49
PHY_RXD3 55
PHY_RXD2 54
PHY_RXD1 51
PHY_RXD0 50
4
PHY XTAL OUT
1
PHY XTAL IN
UG850_c1_14_030513
Feature Descriptions
Name
MDIO
MDC
TX_CLK
TX_CTRL
TXD3
TXD2
TXD1
TXD0
RX_CLK
RX_CTRL
RXD3
RXD2
RXD1
RXD0
31