10/100/1000 Tri-Speed Ethernet Phy - Xilinx KC705 User Manual

Table 1-15: SFP+ Module Control and Status (Cont'd)
SFP_LOS
Note:
1. Default jumper shunt positions are shown in bold text.

10/100/1000 Tri-Speed Ethernet PHY

[Figure
The KC705 board utilizes the Marvell Alaska PHY device (88E1111) U37 for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, and
SGMII interfaces from the FPGA to the PHY
user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P3) with
built-in magnetics.
Table 1-16: PHY Default Interface Mode
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY
address 0b00111 using the settings shown in
via software commands passed over the MDIO interface.
Table 1-17: Board Connections for PHY Configuration Pins
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
SFP Control/Status Signal
1-2, callout 15]
Mode
GMII/MII to copper
Jumper over pins 1-2
(default)
SGMII to copper,
Jumper over pins 2-3
no clock
RGMII Jumper over pins 1-2
Connection on
Pin
Board Definition and Value
V 2.5V
CC
Ground ENA_PAUSE = 0
V 2.5V
CC
V 2.5V
CC
V 2.5V HWCFG_MD[2] = 1
CC
V 2.5V
CC
PHY_LED_RX
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Board Connection
Test Point J8
High = Loss of Receiver Signal
Low = Normal Operation
(Table 1-16). The PHY connection to a
Jumper Settings
J29
Jumper over pins 1-2
Jumper over pins 2-3
Table 1-17. These settings can be overwritten
Bit[2]
Definition and Value
PHYADR[2] = 1 PHYADR[1] = 1
PHYADR[4] = 0
ANEG[3] = 1 ANEG[2] = 1
ANEG[0] = 1 ENA_XC = 1
HWCFG_MD[1] = 1
DIS_FC = 1 DIS_SLEEP = 1
SEL_BDT = 0 INT_POL = 1
Feature Descriptions
J30 J64
No jumper
No jumper
No jumper Jumper on
Bit[1] Bit[0]
Definition and Value
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MD[0] = 1
HWCFG_MD[3] = 1
75/50Ω= 0
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