Cmp2Con — Comparator1 Control Register: Ech, Bank0 - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
4.1.8 CMP2CON — COMPARATOR1 CONTROL REGISTER: ECH, BANK0
Bit Identifier
RESET Value
Read/Write
.7–.5
.4
.3
.2
.1
.0
NOTE:
1. Polarity selection bit (CMP2CON.4) will not affect the interrupt generation logic.
2. Refer to "Programming Tip" in Chapter 14 for proper configuration sequence.
.7 .6
0 0
R/W R/W
Comparator 2 Reference Level Selection Bit
0 0 0 0.45VDD
0 0 1 0.50VDD
0 1 0 0.55VDD
0 1 1 0.60VDD
1 0 0 0.65VDD
1 0 1 0.70VDD
1 1 0 0.75VDD
1 1 1 0.80VDD
Comparator2 Output Polarity Select Bit
0 Does not invert CMP2 output.
1 Inverts CMP2 output.
Comparator2 Enable Bit
0 Disables CMP1.
1 Enables CMP1.
Comparator2 Interrupt Enable Bit
0 Disables CMP1 interrupt.
1 Enables CMP1 interrupt.
Comparator2 Status Bit
0 CMP2_N > CMP2_P
1 CMP2_N < CMP2_P
Comparator2 Pending Bit
0 No interrupt is pending (clears pending bit when write).
1 CMP2 interrupt is pending.
.5 .4
0 0
R/W R/W R/W
4-11
4 CONTROL REGISTERS
.3 .2 .1
0 0 1
R/W R
.0
0
R/W