Cmp0Con — Comparator0 Control Register: Eah, Bank0 - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
4.1.6 CMP0CON — COMPARATOR0 CONTROL REGISTER: EAH, BANK0
Bit Identifier
RESET Value
Read/Write
.7–.5
.4
.3
.2
.1
.0
NOTE:
1. Polarity selection bit (CMP0CON.4) will not affect the interrupt generation logic.
2. Refer to "Programming Tip" in Chapter 14 for proper configuration sequence.
.7 .6
– –
– –
Not used for S3F84B8.
Comparator0 Output Polarity Select Bit
0 Does not invert CMP0 output.
1 Inverts CMP0 output.
Comparator0 Enable Bit
0 Disables CMP0.
1 Enables CMP0.
Comparator0 Interrupt Enable Bit
0 Disables CMP0 interrupt.
1 Enables CMP0 interrupt.
Comparator0 Status Bit
0 CMP0_N > CMP0_P
1 CMP0_N < CMP0_P
Comparator0 Pending Bit
0 No interrupt is pending (clears pending bit when write).
1 CMP0 interrupt is pending.
.5 .4
– 0
– R/W R/W
(1)
(2)
4-9
4 CONTROL REGISTERS
.3 .2 .1
0 0 1
R/W R
.0
0
R/W