Block Diagram Of Pwm Module - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

16.2.6 BLOCK DIAGRAM OF PWM MODULE

PWMCON.7-.6
fxx/64
fxx/8
M
U
fxx/2
X
fxx
Soft Lock
10-bit PWMPDATA Register
CMP1 OUT
Trigger
CMP2 OUT
Soft Lock
Trigger
CMP3 OUT
Trigger
NOTES:
1. CLR&ST (Active high) is valid all the time when PWM is operating. It will clear the counter and restart a new PWM cycle immediately.
2. CLR (Active high) is valid all the time when PWM is operating. It will force the current remaining PWM cycle to low level when PWMCON.5 = 0
or high level when PWMCON.5 = 1.
3. Hard lock (active low) stops the PWM until unlock operation; Soft lock (active low) stops the current PWM and restart PWM at PWMDATA =
PWMPDATA
Hard Lock
PWMCON.3
Overflow
Enable
CLR&ST
10-bit Up-Counter
(Read Only)
10-bit Comparator
PWM Buffer Reg
10-bit PWMDATA Register
PWMCCON.0
PWMCCON.1
PWMCCON.4
PWMCCON.5
PWMCCON.6
PWMCCON.7
Figure 16-5 Functional Block Diagram of PWM Module
(anti-mis-trigger)PWMCON.2
AMTDATA Match
PWMCON.4
Trigger Logic
PWMCON.1
CLR&ST
Pending
PWMCON.0
PWM Logic
Control
Hard Lock
Soft Lock
CMP1 OUT
Trigger
CMP2 OUT
Hard Lock
Trigger
CMP3 OUT
Trigger
16-6
16 10-BIT IH-PWM
CMP0 OUT
PWMCCON.1
PWMCCON.0
PWMINT
"1" When PWMDATA > Counter
"0" When PWMDATA <= Counter
P0.3/PWM
PWMCON.5
PWMCCON.0
PWMCCON.1
PWMCCON.4
PWMCCON.5
PWMCCON.6
PWMCCON.7