Peripheral Interrupt Control Registers - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

5.1.8 PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source, there is one or more corresponding peripheral control register that let you control the
interrupt generated by the related peripheral (see
Interrupt Source
Timer A overflow
Timer A match/capture
CMP3 Interrupt
CMP2 Interrupt
CMP1 Interrupt
CMP0 Interrupt
Timer D overflow
Timer D match
Timer C match
PWM overflow interrupt
P0.0 external interrupt
P0.1 external interrupt
P0.3 external interrupt
P0.4 external interrupt
P0.5 external interrupt
P0.6 external interrupt
ADC Interrupt
NOTE: If an interrupt is un-masked (Enable interrupt level) in the IMR register, a DI instruction should be executed before
clearing the pending bit or changing the enable bit of corresponding interrupt.
Table 5-2 Interrupt Source Control and Data Registers
Interrupt Level
IRQ0
IRQ1
IRQ2
IRQ3
IRQ5
IRQ6
Table 5-2).
Register(s)
TACON
TAPS
TADATA
TACNT
CMP3CON
CMP2CON
CMP1CON
CMP0CON
CMPINT
TDCON
TDPS
TDDATA
TDCNT
PWMCON
PWMCCON
PWMDL
PWMPDATAH/L
PWMDATAH/L
AMTDATA
P0INT
P0CONH/L
P0PND
ADCDATAH/L
ADCON
5-7
5 INTERRUPT STRUCTURE
Location(s)
E1H, BANK1
E2H, BANK1
E3H, BANK1
E4H, BANK1
EDH, BANK0
ECH, BANK0
EBH, BANK0
FAH, BANK0
EEH, BANK0
E9H, BANK1
EAH, BANK1
EBH, BANK1
ECH, BANK1
EFH, BANK0
F0H, BANK0
F1H, BANK0
F2H/F3H, BANK0
F4H/F5H, BANK0
F6H, BANK0
E3H, BANK0
E4H/E5H, BANK0
E6H, BANK0
F8H/F9H, BANK0
FAH, BANK0