Page 1 PRODUCT OVERVIEW SAM88RCRI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements.
Page 2: Product Overview
PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454 FEATURES Timer/Counters SAM88RCRI CPU core One 8-bit basic timer for watchdog function • • • The SAM88RCRI core is low-end version of the • One 8-bit timer/counter with time interval modes current SAM87 core. A/D Converter Memory Nine analog input pins •...
Page 3: Block Diagram
S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0/ADC0/INT0 P0.1/ADC1/INT1 Port 0 P0.2/ADC2 Port I/O and Interrupt Control P0.7/ADC7 Basic Timer P1.0 Timer 0 Port 1 P1.1 88RCRI P1.2 SAMRI CPU ADC0-ADC8 P2.0/T0 P2.1 Port 2 2 KB ROM 208 Byte P0.6/PWM 4 KB ROM Register file P2.6 NOTE:...
Page 4: Pin Assignments
PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454 PIN ASSIGNMENTS /P1.0 P0.0/ADC0/INT0 /P1.1 P0.1/ADC1/INT1 /P1.2 P0.2/ADC2 RESET S3C9452/C9454 P2.0/T0 P0.3/ADC3 P2.1 P0.4/ADC4 (20-DIP-300A/ 20-SOP-375) P2.2 P0.5/ADC5 P2.3 P0.6/ADC6/PWM P2.4 P0.7/ADC7 P2.5 P2.6/ADC8/CLO Figure 1-2. Pin Assignment Diagram (20-Pin DIP/SOP Package)
Page 5 S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW /P1.0 P0.0/ADC0/INT0 /P1.1 P0.1/ADC1/INT1 S3C9452/C9454 /P1.2 P0.2/ADC2 RESET P2.0/T0 P0.3/ADC3 (16-DIP-300A) P2.1 P0.4/ADC4 P2.2 P0.5/ADC5 P2.3 P0.6/ADC6/PWM Figure 1-3. Pin Assignment Diagram (16-Pin DIP Package) S3C9442/C9444 /P1.0 P0.0/ADC0/INT0 (8-DIP-300 /P1.1 P0.1/ADC1/INT1 8-SOP-225) /P1.2 P0.2/ADC2 RESET Figure 1-4. Pin Assignment Diagram (8-Pin DIP/SOP Package)
Page 6: Pin Descriptions
PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454 PIN DESCRIPTIONS Table 1-1. S3C9452/C9454 Pin Descriptions In/Out Pin Description Share Name Type Pins P0.0–P0.7 Bit-programmable I/O port for Schmitt trigger input or ADC0–ADC7 push-pull output. Pull-up resistors are assignable by INT0/INT1 software. Port0 pins can also be used as A/D converter input, PWM output or external interrupt input.
Page 7: Pin Circuits
S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW PIN CIRCUITS P-channel N-channel Figure 1-5. Pin Circuit Type A Figure 1-6. Pin Circuit Type B Pull-up Enable Data Data Circuit Output Type C Output DIsable Disable Digital Input Figure 1-7. Pin Circuit Type C Figure 1-8. Pin Circuit Type D...
Page 8 PRODUCT OVERVIEW S3C9442/C9444/F9444/C9452/C9454/F9454 Open-drain Enable Pull-up enable P2CONH P2CONL P-CH Alternative Data Output P2.x N-CH Output Disable (Input Mode) Digital Input Analog Input Enable Figure 1-9. Pin Circuit Type E Pull-up enable P0CONH P-CH Alternative Data Output P0.x N-CH Output Disable (Input Mode) Digital Input Interrupt Input...
Page 9 S3C9442/C9444/F9444/C9452/C9454/F9454 PRODUCT OVERVIEW Open-drain Enable Pull-up enable P1.x Output Disable (Input Mode) Pull-down enable Digital Input Figure 1-11. Pin Circuit Type E-2...
Page 10: Address Spaces
S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C9442/C9444/C9452/C9454 microcontroller has two kinds of address space: — Internal program memory (ROM) — Internal register file A 12-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file.
Page 11: Program Memory (Rom)
ADDRESS SPACES S3C9442/C9444/F9444/C9452/C9454/F9454 PROGRAM MEMORY (ROM) Normal Operating Mode The S3C9442/C9444/C9452/C9454 have 2-Kbytes (locations 0H–07FFH) or 4-Kbytes (locations 0H–0FFFH) of internal mask-programmable program memory. The first 2-bytes of the ROM (0000H–0001H) are interrupt vector address. Unused locations (0002H–00FFH except 3CH, 3DH, 3EH, 3FH) can be used as normal program memory. 3CH, 3DH, 3EH, 3FH is used smart option ROM cell.
Page 12 S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESS SPACES Smart Option Smart option is the ROM option for starting condition of the chip. The ROM addresses used by smart option are from 003CH to 003FH. The S3C9442/C9444/C9452/9454 only use 003EH, 003FH. Not used ROM address 003CH, 003DH should be initialized to be initialized to 00H. The default value of ROM is FFH (LVR enable, internal RC oscillator).
Page 13 ADDRESS SPACES S3C9442/C9444/F9444/C9452/C9454/F9454 PROGRAMMING TIP — Smart Option Setting << Interrupt Vector Address >> 0000H Vector 00H, INT_9454 ; S3C9454 has only one interrupt vector << Smart Option Setting >> 003CH ; 003CH, must be initialized to 0. ; 003DH, must be initialized to 0. 0E7H ;...
Page 14: Register Architecture
S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESS SPACES REGISTER ARCHITECTURE The upper 64-bytes of the S3C9442/C9444/C9452/C9454's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 192-bytes of internal register file(00H–BFH) is called the general purpose register space. 234 registers in this space can be accessed; 208 are available for general-purpose use.
Page 15 ADDRESS SPACES S3C9442/C9444/F9444/C9452/C9454/F9454 Peripheral Control Registers 64 Bytes of Common Area System Control Registers Working Registers General Purpose Register File 192 Bytes and Stack Area Figure 2-3. Internal Register File Organization...
Page 16: Common Working Register Area (C0H-Cfh)
S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H–CFH) The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file.
Page 17: System Stack
ADDRESS SPACES S3C9442/C9444/F9444/C9452/C9454/F9454 SYSTEM STACK S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9442/C9444/C9452/C9454 architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls and interrupts and data are stored on the stack.
Page 18 S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESS SPACES PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SP ← C0H (Normally, the SP is set to C0H by the SP,#0C0H ;...
Page 19: Addressing Modes
S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.
Page 20: Register Addressing Mode (R)
ADDRESSING MODES S3C9442/C9444/F9444/C9452/C9454/F9454 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses an 16-byte working register space in the register file and an 4-bit register within that space (see Figure 3-2).
Page 21: Indirect Register Addressing Mode (Ir)
S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
Page 22 ADDRESSING MODES S3C9442/C9444/F9444/C9452/C9454/F9454 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory REGISTER Example PAIR Instruction Point to References OPCODE register pair Program 16-bit Memory address points to program Program Memory memory Value used in OPERAND instruction Sample Instructions: CALL @RR2 @RR2 Figure 3-4.
Page 23 S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory 4-Bit 4 LSBs Working OPERAND Register Point to the OPCODE Address working register (1 of 16) Sample Instruction: Value used in OPERAND instruction R6, @R2 Figure 3-5. Indirect Working Register Addressing to Register File...
Page 24 ADDRESSING MODES S3C9442/C9444/F9444/C9452/C9454/F9454 INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File Program Memory 4-Bit Working Register Address Register Next 3 Bits Point Pair OPCODE to working Example instruction register pair references either 16-Bit (1 of 8) program memory or address data memory Program Memory points to LSB Selects...
Page 25: Indexed Addressing Mode (X)
S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
Page 26 ADDRESSING MODES S3C9442/C9444/F9444/C9452/C9454/F9454 INDEXED ADDRESSING MODE (Continued) Program Memory Register File XS (OFFSET) NEXT 3 Bits 4-Bit Working Register Register Address Point to working Pair OPCODE register pair 16-Bit (1 of 8) address added to offset LSB Selects 16-Bit 8-Bit Program Memory Data memory Value used in...
Page 27 S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Program Memory Register File (OFFSET) (OFFSET) Register NEXT 3 Bits 4-Bit Working Pair Register Address Point to working OPCODE 16-Bit register pair address (1 of 8) added to offset LSB Selects 16-Bit 8-Bit Program Memory Datamemory Value used in...
Page 28: Direct Address Mode (Da)
ADDRESSING MODES S3C9442/C9444/F9444/C9452/C9454/F9454 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
Page 29 S3C9442/C9444/F9444/C9452/C9454/F9454 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16-bit immediate address CALL DISPLAY Where DISPLAY is a 16-bit immediate address Figure 3-11.
Page 30: Relative Address Mode (Ra)
ADDRESSING MODES S3C9442/C9444/F9444/C9452/C9454/F9454 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.
Page 31: Control Registers
S3C9442/C9444/F9444/C9452/C9454/F9454 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9442/C9444/C9452/C9454 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs. System and peripheral registers are summarized in Table 4-1.
Page 32 CONTROL REGISTERS S3C9442/C9444/F9444/C9452/C9454/F9454 Table 4-1. System and Peripheral Control Registers Register name Mnemonic Address & Location RESET value (Bit) Address Timer 0 counter register T0CNT Timer 0 data register T0DATA Timer 0 control register T0CON – – – Location D3H is not mapped Clock control register CLKCON –...
Page 33 S3C9442/C9444/F9444/C9452/C9454/F9454 CONTROL REGISTERS Table 4-1. System and Peripheral Control Registers (Continued) Register Name Mnemonic Address Bit Values After RESET Port 0 data register Port 1 data register – – – – – Port 2 data register – Locations E3H–E5H are not mapped Port 0 control register (High byte) P0CONH Port 0 control register...
Page 34 CONTROL REGISTERS S3C9442/C9444/F9444/C9452/C9454/F9454 Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register address Register bit or bit function (hexadecimal) Full Register name mnemonic FLAGS - System Flags Register Bit Identifier Value RESET Read/Write Carry Flag (C) Operation dose not generate a carry or borrow condition Operation generates carry-out or borrow into high-order bit7...
Page 35 S3C9442/C9444/F9444/C9452/C9454/F9454 CONTROL REGISTERS ADCON — A/D Converter Control Register Bit Identifier Value Read/Write .7–.4 A/D Converter Input Pin Selection Bits ADC0 (P0.0) ADC1 (P0.1) ADC2 (P0.2) ADC3 (P0.3)/ In S3C9444, connected with GND internally ADC4 (P0.4)/ In S3C9444, connected with GND internally ADC5 (P0.5)/ In S3C9444, connected with GND internally ADC6 (P0.6)/ In S3C9444, connected with GND internally ADC7 (P0.7)/ In S3C9444, connected with GND internally...
Page 36 CONTROL REGISTERS S3C9442/C9444/F9444/C9452/C9454/F9454 BTCON — Basic Timer Control Register Bit Identifier Value Read/Write .7–.4 Watchdog Timer Function Enable Bit Disable watchdog timer function Others Enable watchdog timer function .3–.2 Basic Timer Input Clock Selection Code /4096 /1024 /128 Invalid setting Basic Timer 8-Bit Counter Clear Bit No effect Clear the basic timer counter value...
Page 37: Clock Control Register
S3C9442/C9444/F9444/C9452/C9454/F9454 CONTROL REGISTERS CLKCON — Clock Control Register Bit Identifier Value – – – – – Read/Write – – – – – Oscillator IRQ Wake-up Function Enable Bit Enable IRQ for main system oscillator wake-up function Disable IRQ for main system oscillator wake-up function .6–.5 Not used for S3C9442/C9444/C9452/C9454 .4–.3...
Page 38 CONTROL REGISTERS S3C9442/C9444/F9444/C9452/C9454/F9454 FLAGS — System Flags Register Bit Identifier Value – – – – Read/Write – – – – Carry Flag (C) Operation does not generate a carry or borrow condition Operation generates a carry-out or borrow into high-order bit 7 Zero Flag (Z) Operation result is a non-zero value Operation result is zero...
Page 39 S3C9442/C9444/F9444/C9452/C9454/F9454 CONTROL REGISTERS P0CONH — Port 0 Control Register (High Byte) Bit Identifier Value Read/Write .7–.6 Port 0, P0.7/INT7 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output A/D converter input (ADC7); Schmitt trigger input off .5–.4 Port 0, P0.6/ADC6/PWM Configuration Bits Schmitt trigger input;...
Page 40 CONTROL REGISTERS S3C9442/C9444/F9444/C9452/C9454/F9454 P0CONL — Port 0 Control Register (Low Byte) Bit Identifier Value Read/Write .7–.6 Port 0, P0.3/INT3 Configuration Bits Schmitt trigger input Schmitt trigger input; pull-up enable Push-pull output A/D converter input (ADC3); Schmitt trigger input off .5–.4 Port 0, P0.2/ADC2 Configuration Bits Schmitt trigger input Schmitt trigger input;...
Page 41 S3C9442/C9444/F9444/C9452/C9454/F9454 CONTROL REGISTERS P0PND — Port 0 Interrupt Pending Register Bit Identifier Value – – – – Read/Write – – – – .7–.4 Not used for the S3C9442/C9444/C9452/C9454 Port 0.1/ADC1/INT1 Interrupt Enable Bit INT1 falling edge interrupt disable INT1 falling edge interrupt enable Port 0.1/ADC1/INT1 Interrupt Pending Bit No interrupt pending (when read) Pending bit clear (when write)
Page 42 CONTROL REGISTERS S3C9442/C9444/F9444/C9452/C9454/F9454 P1CON — Port 1 Control Register Bit Identifier Value – – Read/Write – – Part 1.1 N-channel open-drain Enable Bit Configure P1.1 as a push-pull output Configure P1.1 as a n-channel open-drain output Port 1.0 N-channel open-drain Enable Bit Configure P1.0 as a push-pull output Configure P1.0 as a n-channel open-drain output .5–.4...
Page 43 S3C9442/C9444/F9444/C9452/C9454/F9454 CONTROL REGISTERS P2CONH — Port 2 Control Register (High Byte) Bit Identifier Value – Read/Write – Not used for the S3C9442/C9444/C9452/C9454 .6–.4 Port 2, P2.6/ADC8/CLO Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input ADC input Push-pull output Open-drain output;...
Page 44 CONTROL REGISTERS S3C9442/C9444/F9444/C9452/C9454/F9454 P2CONL — Port 2 Control Register (Low Byte) Bit Identifier Value Read/Write .7–.6 Part 2, P2.3 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output .5–.4 Port 2, P2.2 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output...
Page 45: Pwm Control Register
S3C9442/C9444/F9444/C9452/C9454/F9454 CONTROL REGISTERS PWMCON — PWM Control Register Bit Identifier Value – Read/Write – .7–.6 PWM Input Clock Selection Bits Not used for S3C9442/C9444/C9452/C9454 PWMDATA Reload Interval Selection Bit Reload from 8-bit up counter overflow Reload from 6-bit up counter overflow PWM Counter Clear Bit No effect Clear the PWM counter (when write)
Page 46 CONTROL REGISTERS S3C9442/C9444/F9444/C9452/C9454/F9454 STOPCON — STOP Mode Control Register Bit Identifier Value Read/Write .7–.0 Watchdog Timer Function Enable Bit 10100101 Enable STOP instruction Other value Disable STOP instruction NOTE: When STOPCON register is not #0A5H value, if you use STOP instruction, PC is changed to reset address. —...
Page 47 S3C9442/C9444/F9444/C9452/C9454/F9454 CONTROL REGISTERS T0CON — TIMER 0 Control Register Bit Identifier Value – – – Read/Write – – – .7–.6 Timer 0 Input Clock Selection Bits /256 .5–.4 Not used for the S3C9442/C9444/C9452/C9454 Timer 0 Counter Clear Bit No effect Clear the timer 0 counter (when write) Not used for the S3C9442/C9444/C9452/C9454 Timer 0 Interrupt Enable Bit...
Page 48: Interrupt Structure
S3C9442/C9444/F9444/C9452/C9454/F9454 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through an interrupt vector which is assigned in ROM address 0000H. VECTOR SOURCES 0000H 0001H NOTES: 1.
Page 49: Enable/Disable Interrupt Instructions (Ei, Di)
INTERRUPT STRUCTURE S3C9442/C9444/F9444/C9452/C9454/F9454 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The system mode register, SYM (DFH), is used to enable and disable interrupt processing. SYM.2 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.2. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing.
Page 50: Interrupt Source Service Sequence
S3C9442/C9444/F9444/C9452/C9454/F9454 INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3.
Page 51 INTERRUPT STRUCTURE S3C9442/C9444/F9444/C9452/C9454/F9454 S3C9442/C9444/C9452/C9454 INTERRUPT STRUCTURE The S3C9442/C9444/C9452/C9454 microcontroller has four peripheral interrupt sources: — PWM overflow — Timer 0 match — P0.0 external interrupt — P0.1 external interrupt Vector Pending Bits Enable/Disable Source Timer 0 match T0CON.0 T0CON.1 PWM Overflow PWMCON.0 PWMCON.1 0000H...
Page 52: Sam88Rcri Instruction Set
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET SAM88RCRI INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8-bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file.
Page 53 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst,src Load dst,src Load program memory dst,src Load external data memory LDCD dst,src Load program memory and decrement LDED dst,src Load external data memory and decrement LDCI dst,src Load program memory and increment...
Page 54 S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL Call procedure IRET Interrupt return cc,dst Jump on condition code Jump unconditional cc,dst Jump relative on condition code Return Bit Manipulation Instructions dst,src Test complement under mask dst,src Test under mask...
Page 55: Flags Register (Flags)
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4–FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.
Page 56: Instruction Set Notation
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation – Value is unaffected Value is undefined Table 6-3.
Page 57 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Working register pair RRp (p = 0, 2, 4, ..., 14) Register or working register reg or Rn (reg = 0–255, n = 0–15) Register pair or working register pair...
Page 58 S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IRR1 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2...
Page 59 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – r1,R2 r2,R1 cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ IDLE ↓ ↓ ↓ ↓ ↓ ↓ STOP IRET ↓ ↓ ↓ ↓ ↓...
Page 60: Condition Codes
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal.
Page 61: Instruction Descriptions
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM87Ri instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...
Page 62: Adc - Add With Carry
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Add with Carry dst,src dst ← dst + src + c Operation: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
Page 63 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: Set if there is a carry from the most significant bit of the result;...
Page 64 S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...
Page 65: Call Procedure
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 CALL — Call Procedure CALL ← Operation: SP – 1 ← ← SP –1 ← ← The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
Page 66: Ccf - Complement Carry Flag
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: Complemented.
Page 67 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Clear dst ← "0" Operation: The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: →...
Page 68 S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0".
Page 69 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Compare dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: Set if a "borrow"...
Page 70: Dec - Decrement
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is – 128 (80H) and result value is + 127 (7FH);...
Page 71: Di - Disable Interrupts
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Disable Interrupts SYM (2) ← 0 Operation: Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
Page 72: Ei - Enable Interrupts
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Enable Interrupts SYM (2) ← 1 Operation: An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
Page 73: Idle - Idle Operation
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: Bytes Cycles...
Page 74: Inc - Increment
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. Flags: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is dst value is + 127 (7FH) and result is –...
Page 75: Iret - Interrupt Return
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 IRET — Interrupt Return IRET IRET FLAGS ← @SP Operation: SP ← SP + 1 PC ← @SP SP ← SP + 2 SYM(2) ← 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter.
Page 76 S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.
Page 77: Jr - Jump Relative
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...
Page 78 S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc src | opc r = 0 to F dst | src...
Page 79 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Load (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0,#10H R0 = 10H →...
Page 80: Load Memory
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes "Irr"...
Page 81 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
Page 82: Load Memory And Decrement
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
Page 83: Load Memory And Increment
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 LDCI/LDEI — LOAD MEMORY AND INCREMENT LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
Page 84: Nop - No Operation
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycles...
Page 85 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...
Page 86: Pop - Pop From Stack
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.
Page 87: Push To Stack
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 PUSH — Push To Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.
Page 88: Rcf - Reset Carry Flag
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: Given: C = "1"...
Page 89 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
Page 90: Rl - Rotate Left
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
Page 91: Rlc - Rotate Left Through Carry
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Rotate Left Through Carry dst (0) ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...
Page 92: Rr - Rotate Right
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
Page 93: Rrc - Rotate Right Through Carry
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Rotate Right Through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...
Page 94: Sbc - Subtract With Carry
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Subtract With Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
Page 95: Scf - Set Carry Flag
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. Flags: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: The statement sets the carry flag to logic one.
Page 96: Sra - Shift Right Arithmetic
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.
Page 97: Stop - Stop Operation
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input.
Page 98: Sub - Subtract
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
Page 99: Test Complement Under Mask
SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Test Complement Under Mask dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
Page 100: Tm - Test Under Mask
S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.
Page 101 SAM88RCRI INSTRUCTION SET S3C9442/C9444/F9444/C9452/C9454/F9454 — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...
Page 102: Clock Circuit
S3C9442/C9444/F9444/C9452/C9454/F9454 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW By smart option (3FH.1–.0 in ROM), user can select internal RC oscillator or external oscillator. In using internal oscillator, X (P1.0), X (P1.1) can be used by normal I/O pins. An internal RC oscillator source provides a typical 3.2 MHz or 0.5 MHz (in V = 5 V) depending on smart option.
Page 103: Clock Status During Power-Down Modes
CLOCK CIRCUIT S3C9442/C9444/F9444/C9452/C9454/F9454 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows: — In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file and current system register values are retained.
Page 104 S3C9442/C9444/F9444/C9452/C9454/F9454 CLOCK CIRCUIT Smart option (3F.1-0 in ROM) Stop Instruction CLKCON.4-.3 Internal RC oscillator (3.2 MHz) Oscillator Stop Internal RC oscillator (0.5 MHz) Selected CPU Clock External crystal/ ceramic oscillator Oscillator Wake-up 1/16 External RC Noise oscillator Filter P2.6/CLO CLKCON.7 P2CONH.6-.4 INT Pin NOTE:...
Page 105: System Reset
S3C9442/C9444/F9444/C9452/C9454/F9454 and POWER-DOWN RESET and POWER-DOWN RESET SYSTEM RESET OVERVIEW By smart option (3EH.7 in ROM), user can select internal (LVR) or external . In using internal RESET RESET (LVR), pin (P1.2) can be used by normal I/O pin. RESET RESET The S3C9442/C9444/C9452/C9454 can be in four ways:...
Page 106 and POWER-DOWN S3C9442/C9444/F9444/C9452/C9454/F9454 RESET NOTE To program the duration of the oscillation stabilization interval, you must make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing "1010B"...
Page 107: Power-Down Modes
S3C9442/C9444/F9444/C9452/C9454/F9454 and POWER-DOWN RESET POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 100 µA.
Page 108: Hardware Reset Values
and POWER-DOWN S3C9442/C9444/F9444/C9452/C9454/F9454 RESET HARDWARE RESET VALUES Table 8-1 lists the values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation in normal operating mode. — A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. —...
Page 109 S3C9442/C9444/F9444/C9452/C9454/F9454 and POWER-DOWN RESET Table 8-1. Register Values After a Reset (Continued) Register Name Mnemonic Address Bit Values After RESET Port 0 data register Port 1 data register – – – – – Port 2 data register – Locations E3H–E5H are not mapped Port 0 control register (High byte) P0CONH Port 0 control register...
Page 110 and POWER-DOWN S3C9442/C9444/F9444/C9452/C9454/F9454 RESET PROGRAMMING TIP — Sample S3C9454 Initialization Routine ;--------------<< Interrupt Vector Address >> 0000H VECTOR 00H,INT_9454 ; S3C9454 has only one interrupt vector ;--------------<< Smart Option >> 003CH ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 0E7H ;...
Page 111 S3C9442/C9444/F9444/C9452/C9454/F9454 and POWER-DOWN RESET PROGRAMMING TIP — Sample S3C9454 Initialization Routine (Continued) ;--------------<< Main loop >> MAIN: ; Start main loop BTCON,#02H ; Enable watchdog function ; Basic counter (BTCNT) clear • • CALL KEY_SCAN • • • CALL LED_DISPLAY •...
Page 112 and POWER-DOWN S3C9442/C9444/F9444/C9452/C9454/F9454 RESET PROGRAMMING TIP — Sample S3C9454 Initialization Routine (Continued) ;--------------<< Interrupt Service Routines >> ; Interrupt enable bit and pending bit check INT_9454: T0CON,#00000010B ; Timer0 interrupt enable check Z,NEXT_CHK1 T0CON,#00000001B ; If timer0 interrupt was occurred, NZ,INT_TIMER0 ;...
Page 113 S3C9442/C9444/F9444/C9452/C9454/F9454 and POWER-DOWN RESET PROGRAMMING TIP — Sample S3C9454 Initialization Routine (Continued) ;--------------< External interrupt0 service routine > • INT0_INT: • P0PND,#11111110B ; INT0 Pending bit clear IRET ; Interrupt return ;--------------< External interrupt1 service routine > • INT1_INT: • P0PND,#11111011B ;...
Page 114 S3C9442/C9444/F9444/C9452/C9454/F9454 I/O PORTS I/O PORTS OVERVIEW The S3C9442/C9444/C9452/C9454 has three I/O ports: with 18 pins total. You access these ports directly by writing or reading port data register addresses. All ports can be configured as LED drive. (High current output: typical 10 mA) Table 9-1.
Page 115: Port Data Registers
I/O PORTS S3C9442/C9444/F9444/C9452/C9454/F9454 PORT DATA REGISTERS Table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics. Data registers for ports 0-2 have the structure shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Mnemonic Port 0 data register...
Page 116 S3C9442/C9444/F9444/C9452/C9454/F9454 I/O PORTS PORT 0 Port 0 is a bit-programmable, general-purpose, I/O ports. You can select normal input or push-pull output mode. In addition, you can configure a pull-up resistor to individual pins using control register settings. It is designed for high-current functions such as LED direct drive. Part 0 pins can also be used as alternative functions (ADC input, external interrupt input and PWM output).
Page 117 I/O PORTS S3C9442/C9444/F9444/C9452/C9454/F9454 Port 0 Control Register (High Byte) E6H, R/W [.7-.6] Port, P0.7/ADC7 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = A/D converter input (ADC7); schmitt trigger input off [.5-.4] Port 0, P0.6/ADC6/PWM Configuration Bits 0 0 = Schmitt trigger input;...
Page 118 S3C9442/C9444/F9444/C9452/C9454/F9454 I/O PORTS Port 0 Control Register (Low Byte) E7H, R/W [.7-.6] Port 0, P0.3/ADC3 Configuration Bits 0 0 = Schmitt trigger input 0 1 = Schmitt trigger input; pull-up enable 1 0 = Push-pull output 1 1 = A/D converter input (ADC3); Schmitt trigger input off [.5-.4] Port 0, P0.2/ADC2 Configuration Bits 0 0 = Schmitt trigger input 0 1 = Schmitt trigger input;...
Page 119 I/O PORTS S3C9442/C9444/F9444/C9452/C9454/F9454 Port 0 Interrupt Pending Register E8H, R/W [.7-.4] Not used for S3C9442/C9444/C9452/C9454 [.3] Port 0.1/ADC1/INT1, Interrupt Enable Bit 0 = INT1 falling edge interrupt disable 1 = INT1 falling edge interrupt enable [.2] Port 0.1/ADC1/INT1, Interrupt Pending Bit 0 = No interrupt pending (when read) 0 = Pending bit clear (when write) 1 = Interrupt is pending (when read)
Page 120 S3C9442/C9444/F9444/C9452/C9454/F9454 I/O PORTS PORT 1 Port 1, is a 3-bit I/O port with individually configurable pins. It can be used for general I/O port (Schmitt trigger input mode, push-pull output mode or n-channel open-drain output mode). In addition, you can configure a pull- up and pull-down resistor to individual pin using control register settings.
Page 121 I/O PORTS S3C9442/C9444/F9444/C9452/C9454/F9454 Port 1 Control Register E9H, R/W [.7] Port 1.1 N-channel open-drain Enable Bit 0 = Configure P1.1 as a push-pull output 1 = Configure P1.1 as a n-channel open-drain output [.6] Port 1.0 N-channel open-drain Enable Bit 0 = Configure P1.0 as a push-pull output 1 = Configure P1.0 as a N-channel open-drain output [.5-.4] Not used for S3C9442/C9444/C9452/C9454...
Page 122 S3C9442/C9444/F9444/C9452/C9454/F9454 I/O PORTS PORT 2 Port 2 is a 7-bit I/O port with individually configurable pins. It can be used for general I/O port (schmitt trigger input mode, push-pull output mode or N-channel open-drain output mode). You can also use some pins of port 2 ADC input, CLO output and T0 clock output.
Page 123 I/O PORTS S3C9442/C9444/F9444/C9452/C9454/F9454 Port 2 Control Register (High Byte) EAH, R/W [.7] Not sued for S3C9442/C9444/C9452/C9454 [.6-.4] Port 2, P2.6/ADC8/CLO Configuration Bits 0 0 0 = Schmitt trigger input; pull-up enable 0 0 1 = Schmitt trigger input 0 1 x = ADC input 1 0 0 = Push-pull output 1 0 1 = Open-drain output;...
Page 124 S3C9442/C9444/F9444/C9452/C9454/F9454 I/O PORTS Port 2 Control Register (Low Byte) EBH, R/W [.7-.6] Port 2, P2.3 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = Open-drain output [.5-.4] Port 2, P2.2 Configuration Bits 0 0 = Schmitt trigger input;...
Page 125: Module Overview
S3C9442/C9444/F9444/C9452/C9454/F9454 BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 MODULE OVERVIEW The S3C9442/C9444/C9452/C9454 has two default timers: an 8-bit basic timer, one 8-bit general-purpose timer/counter, called timer 0. Basic Timer (BT) You can use the basic timer (BT) in two different ways: —...
Page 126: Basic Timer Control Register (Btcon)
BASIC TIMER and TIMER 0 S3C9442/C9444/F9444/C9452/C9454/F9454 BASIC TIMER (BT) BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. A reset clears BTCON to "00H".
Page 127: Basic Timer Function Description
S3C9442/C9444/F9444/C9452/C9454/F9454 BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than "1010B" (The "1010B" value disables the watchdog function). A reset clears BTCON to "00H", automatically enabling the watchdog timer function.
Page 128 BASIC TIMER and TIMER 0 S3C9442/C9444/F9444/C9452/C9454/F9454 Oscillation Stabilization Time Normal Operating mode 0.8 V Reset Release Voltage RESET trst Internal Reset Release 0.8 V Oscillator Oscillator Stabilization Time BTCNT clock 10000B BTCNT value 00000B = (4096x16)/f WAIT Basic timer increment and CPU operations are IDLE mode NOTE: Duration of the oscillator stabilization wait time, t , when it is released by a...
Page 129 S3C9442/C9444/F9444/C9452/C9454/F9454 BASIC TIMER and TIMER 0 Normal STOP Mode Oscillation Stabilization Time Normal Operating Operating Mode Mode STOP Instruction STOP Mode Execution Release Signal External Interrupt RESET STOP Release Signal Oscillator BTCNT clock 10000B BTCNT 00000B Value WAIT Basic Timer Increment NOTE: Duration of the oscillator stabilzation wait time, t , it is released by an WAIT...
Page 130 BASIC TIMER and TIMER 0 S3C9442/C9444/F9444/C9452/C9454/F9454 PROGRAMMING TIP — Configuring the Basic Timer This example shows how to configure the basic timer to sample specification. 0000H VECTOR 00H,INT_9454 ; S3C9454 has only one interrupt vector ;--------------<< Smart Option >> 003CH ;...
Page 131 S3C9442/C9444/F9444/C9452/C9454/F9454 BASIC TIMER and TIMER 0 TIMER 0 TIMER 0 CONTROL REGISTERS (T0CON) The timer 0 control register, T0CON, is used to select the timer 0 operating mode (interval timer) and input clock frequency, to clear the timer 0 counter, and to enable the T0 match interrupt. It also contains a pending bit for T0 match interrupts.
Page 132: Timer 0 Function Description
BASIC TIMER and TIMER 0 S3C9442/C9444/F9444/C9452/C9454/F9454 TIMER 0 FUNCTION DESCRIPTION Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the Timer 0 reference data register, T0DATA. The match signal generates a Timer 0 match interrupt (T0INT, vector 00H) and then clears the counter.
Page 133 S3C9442/C9444/F9444/C9452/C9454/F9454 BASIC TIMER and TIMER 0 Match Match Match Compare Value (T0DATA) Match Match Match Match Up Counter Value (T0CNT) Clear Clear Clear Count start T0CON.3 1 T0DATA Value change Counter Clear (T0CON.3) Interrupt Request (T0CON.0) T0 Match Output (P2.0) Figure 10-6.
Page 134 BASIC TIMER and TIMER 0 S3C9442/C9444/F9444/C9452/C9454/F9454 Bit 1 RESET STOP Basic Timer Control Register Bits 3, 2 (Write '1010xxxxB' to disable.) Data Bus Clear 1/4096 RESET 8-Bit Up Counter 1/1024 (BTCNT, Read-Only) 1/128 When BTCNT.4 is set after releasing from RESET or STOP mode, CPU clock starts.
Page 135 S3C9442/C9444/F9444/C9452/C9454/F9454 BASIC TIMER and TIMER 0 PROGRAMMING TIP1 – Configuring Timer 0 (Interval Mode) The following sample program sets Timer 0 to interval timer mode. 0000H VECTOR 00H,INT_9454 ; S3C9454 has only one interrupt vector 003CH ; 003CH, must be initialized to 0 ;...
Page 136 BASIC TIMER and TIMER 0 S3C9442/C9444/F9444/C9452/C9454/F9454 PROGRAMMING TIP1 – Configuring Timer 0 (Interval Mode) (Continued) LED_DISPLAY: • • • JOB: • • • ;--------------<< Interrupt Service Routines >> INT_9454: T0CON,#00000010B ; Interrupt enable check Z,NEXT_CHK1 T0CON,#00000001B ; If timer 0 interrupt was occurred, NZ,INT_TIMER0 ;...
Page 137: Function Description
S3C9442/C9444/F9444/C9452/C9454/F9454 8-BIT PWM 8-BIT PWM (PULSE WIDTH MODULATION OVERVIEW This microcontroller has the 8-bit PWM circuit. The operation of all PWM circuit is controlled by a single control register, PWMCON. The PWM counter is a 8-bit incrementing counter. It is used by the 8-bit PWM circuits. To start the counter and enable the PWM circuits, you set PWMCON.2 to "1".
Page 138 8-BIT PWM S3C9442/C9444/F9444/C9452/C9454/F9454 PWM data and extension registers PWM (duty) data registers, located in F2H, determine the output value generated by each 8-bit PWM circuit. To program the required PWM output, you load the appropriate initialization values into the 6-bit reference data register (PWMDATA.7–.2) and the 2-bit extension data register (PWMDATA.1–.0).
Page 139 S3C9442/C9444/F9444/C9452/C9454/F9454 8-BIT PWM Table 11-2. PWM output "stretch" Values for Extension Data Register (PWMDATA.1–.0) PWMDATA Bit (Bit1–Bit0) "Stretched" Cycle Number – 1, 3 1, 2, 3 4 MHz Clock: 000000xxB 250 ns 250 ns 000001xxB Data Register Values: 100000xxB (PWMDATA) 8 ms 8 ms 111111xxB...
Page 140 8-BIT PWM S3C9442/C9444/F9444/C9452/C9454/F9454 PWM Clock: 4 MHz 500 ns 000010xxB PWMDATA : 0000 1001B Basic Extended waveform waveform 1st 2nd 3th 1st 2nd 3th 4 MHz 750 ns Figure 11-2. 8-Bit Extended PWM Waveform 11-4...
Page 141 S3C9442/C9444/F9444/C9452/C9454/F9454 8-BIT PWM PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is located at register address F3H. PWMCON is used the 8-bit PWM modules. Bit settings in the PWMCON register control the following functions: — PWM counter clock selection —...
Page 142 8-BIT PWM S3C9442/C9444/F9444/C9452/C9454/F9454 PWMCON.6-.7 From 8-bit up counter (7:6) From 8-bit up counter (5:0) 2-bit 6-bit Counter Counter PWMCON.2 "1" When REG > Count 6-bit Comparator P0.6/PWM "1" When REG = Count 6-bit Data Buffer Extension Control Logic Extension Data Buffer 6-bit Data bit7-2...
Page 143 S3C9442/C9444/F9444/C9452/C9454/F9454 8-BIT PWM PROGRAMMING TIP — Programming the PWM Module to Sample Specifications ;--------------<< Interrupt Vector Address >> 0000H VECTOR 00H,INT_9454 ; S3C9454 has only one interrupt vector ;--------------<< Smart Option >> 003CH ; 003CH, must be initialized to 0. ;...
Page 144 8-BIT PWM S3C9442/C9444/F9444/C9452/C9454/F9454 PROGRAMMING TIP — Programming the PWM Module to Sample Specifications (Continued) INT_PWM: ; PWM interrupt service routine • • • PWMCON,#11110110B ; pending bit clear IRET • • 11-8...
Page 145 S3C9442/C9444/F9444/C9452/C9454/F9454 A/D CONVERTER A/D CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the nine input channels to equivalent 10-bit digital values. The analog input level must lie between the and V values.
Page 146 A/D CONVERTER S3C9442/C9444/F9444/C9452/C9454/F9454 USING A/D PINS FOR STANDARD DIGITAL INPUT The ADC module's input pins are alternatively used as digital input in port 0 and P2.6. A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address F7H. ADCON has four functions: —...
Page 147: Internal Reference Voltage Levels
S3C9442/C9444/F9444/C9452/C9454/F9454 A/D CONVERTER INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range V to V Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step.
Page 148: Conversion Timing
A/D CONVERTER S3C9442/C9444/F9444/C9452/C9454/F9454 (Preliminary Spec) ADC0N.0 50 ADC clock Conversion Start ADDATA Privious ADDATAH (8-bit) + ADDATAL (2-bit) Valid Value data Set-up time 40 clock 10 clock Figure 12-4. A/D Converter Timing Diagram CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up A/D conversion.
Page 149 S3C9442/C9444/F9444/C9452/C9454/F9454 (Preliminary Spec) A/D CONVERTER Analog ADC0-ADC8 Input Pin S3C9442/C9444/ C9452/C9454 Figure 12-5. Recommended A/D Converter Circuit for Highest Absolute Accuracy 12-5...
Page 150 A/D CONVERTER S3C9442/C9444/F9444/C9452/C9454/F9454 (Preliminary Spec) Programming Tip– Configuring A/D Converter 0000H VECTOR 00H,INT_9454 ; S3C9454 has only one interrupt vector 003CH ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 0E7H ; 003EH, enable LVR (2.3 V) ;...
Page 151 S3C9442/C9444/F9444/C9452/C9454/F9454 (Preliminary Spec) A/D CONVERTER Programming Tip– Configuring A/D Converter (Continued) CONV_LOOP: TM ADCON,#00001000B ; Check EOC flag Z,CONV_LOOP ; If EOC flag=0, jump to CONV_LOOP until EOC flag=1 R0,ADDATAH ; High 8 bits of conversion result are stored ; to ADDATAH register R1,ADDATAL ;...
Page 152: Electrical Data
S3C9442/C9444/F9444/C9452/C9454/F9454 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the following S3C9442/C9444/C9452/C9454 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Input Timing Measurement Points — Oscillator characteristics —...
Page 153 ELECTRICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 Table 13-1. Absolute Maximum Ratings ° = 25 Parameter Symbol Conditions Rating Unit Supply voltage – – 0.3 to + 6.5 – 0.3 to V + 0.3 Input voltage All ports – 0.3 to V + 0.3 Output voltage All output ports Output current high...
Page 154 S3C9442/C9444/F9444/C9452/C9454/F9454 ELECTRICAL DATA Table 13-2. DC Electrical Characteristics ° ° = – 40 C to + 85 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Input high Ports 0, 1, 2 and = 2.0 to 5.5 V 0.8 V –...
Page 155 ELECTRICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 Table 13-3. AC Electrical Characteristics ° ° = – 40 C to + 85 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Interrupt input – – INT0, INT1 INTL = 5 V ± 10 % low width input –...
Page 156 S3C9442/C9444/F9444/C9452/C9454/F9454 ELECTRICAL DATA Table 13-4. Oscillator Characteristics ° ° = – 40 C to + 85 Oscillator Clock Circuit Test Condition Unit = 4.5 to 5.5 V Main crystal or – ceramic = 2.7 to 4.5 V – = 2.0 to 2.7 V –...
Page 157 ELECTRICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 CPU Clock 10 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1 MHz Supply Voltage (V) Figure 13-2. Operating Voltage Range A = 0.2 V B = 0.4 V C = 0.6 V D = 0.8 V 0.3 V 0.7 V Figure 13-3.
Page 158 S3C9442/C9444/F9444/C9452/C9454/F9454 ELECTRICAL DATA Table 13-6. Data Retention Supply Voltage in Stop Mode ° ° = – 40 C to + 85 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Data retention Stop mode – DDDR supply voltage Stop mode;...
Page 159 ELECTRICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 Table 13-7. A/D Converter Electrical Characteristics ° ° = – 40 C to + 85 C, V = 2.7 V to 5.5 V, V = 0 V) Parameter Symbol Test Conditions Unit ± 3 = 5.12 V Total accuracy –...
Page 160 S3C9442/C9444/F9444/C9452/C9454/F9454 ELECTRICAL DATA Table 13-8. LVR Circuit Characteristics ° = 25 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Low voltage reset – – LVR hysteresis voltage – – Power supply voltage (note) rise time Power supply voltage off time NOTE: 2 /fx ( = 6.55 ms at fx = 10 MHz)
Page 161: Mechanical Data
MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C9452/C9454 is available in a 20-pin DIP package (Samsung: 20-DIP-300A), a 20-pin SOP package (Samsung: 20-SOP-375), a 16-pin DIP package (Samsung: 16-DIP-300A). Package dimensions are shown in Figure 15-1, 15-2, and 15-3. The S3C9442/C9444 is available in a 8-pin DIP package (SAMSUNG 8-DIP-300A), a 8-pin SOP package (SAMSUNG 8-SOP-225).
Page 162 MECHANICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 20-SOP-375 + 0.10 0.203 - 0.05 13.14 MAX ± 0.20 12.74 0.10 MAX 1.27 (0.66) + 0.10 0.40 - 0.05 NOTE: Dimensions are in millimeters. Figure 14-2. 20-SOP-375 Package Dimensions 14-2...
Page 163 S3C9442/C9444/F9444/C9452/C9454/F9454 MECHANICAL DATA 0-15 16-DIP-300A 19.80 MAX 19.40 ± 0.20 0.46 ± 0.10 2.54 (0.81) 1.50 ± 0.10 NOTE: Dimensions are in millimeters. Figure 14-3. 16-DIP-300A Package Dimensions 14-3...
Page 164 MECHANICAL DATA S3C9442/C9444/F9444/C9452/C9454/F9454 0-15 8-DIP-300 9.60 MAX 9.20 ± 0.20 2.54 (0.79) ± 0.10 0.46 ± 0.10 1.52 NOTE: Dimensions are in millimeters. Figure 14-4. 8-DIP-300 Package Dimensions 14-4...
Page 165 S3C9442/C9444/F9444/C9452/C9454/F9454 MECHANICAL DATA 8-SOP-225 + 0.10 0.15 - 0.05 5.13 MAX ± 0.20 4.92 0.10 MAX 1.27 (0.56) 0.41 ± 0.10 NOTE: Dimensions are in millimeters. Figure 14-5. 8-SOP-225 Package Dimensions 14-5...
Page 166 S3C9442/C9444/F9444/C9452/C9454/F9454 S3F9444/F9454 MTP S3F9444/F9454 MTP OVERVIEW The S3F9444/F9454 single-chip CMOS microcontroller is the MTP (Multi Time Programmable) version of the S3C9442/C9444/C9452/C9454 microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format. The S3F9444/F9454 is fully compatible with the S3C9442/C9444/C9452/C9454, in function, in D.C.
Page 167 S3F9444/F9454 MTP S3C9442/C9444/F9444/C9452/C9454/F9454 /P1.0 P0.0/ADC0/INT0/SCL /P1.1 P0.1/ADC1/INT1/SDA P0.2/ADC2 /P1.2 RESET S3F9454 T0/P2.0 P0.3/ADC3 P0.4/ADC4 P2.1 P0.5/ADC5 P2.2 P0.6/ADC6/PWM P2.3 NOTE: The bolds indicate MTP pin name. Figure 15-2. Pin Assignment Diagram (16-Pin Package) P0.0/ADC0/INT0/SCL /P1.0 S3F9444 P0.1/ADC1/INT1/SDA /P1.1 /P1.2 P0.2/ADC2 RESET NOTE: The bolds indicate MTP pin name.
Page 168: Operating Mode Characteristics
S3C9442/C9444/F9444/C9452/C9454/F9454 S3F9444/F9454 MTP Table 15-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin Name Pin No. Function P0.1 18 (20-pin) Serial data pin (output when reading, Input 14 (16-pin) when writing) Input and push-pull output port can be assigned P0.0 19 (20-pin)
Page 169: Development Tools
SMDS2+, for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. SHINE Samsung Host Interface for in-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+.
Page 170: Target Boards
DEVELOPMENT TOOLS S3C9442/C9444/F9444/C9452/C9454/F9454 TARGET BOARDS Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. MTPs Multi times programmable microcontrollers (MTPs) are under development for S3C9442/C9444/C9452/C9454 microcontroller. IBM-PC AT or Compatible RS-232C SMDS2+ Target...
Page 171 S3C9442/C9444/F9444/C9452/C9454/F9454 DEVELOPMENT TOOLS TB9442/4/9452/4 TARGET BOARD The TB9442/4/9452/4 target board is used for the S3C9442/C9444/C9452/C9454 microcontrollers. It is supported by the SMDS2+ development systems. TB9442/4/9452/4 To User_V RESET Idle Stop J101 128 QFP S3E9450 EVA Chip External 8 pin DIP switch Triggers SMDS SMDS2+...
Page 172 DEVELOPMENT TOOLS S3C9442/C9444/F9444/C9452/C9454/F9454 Table 16-1. Power Selection Settings for TB9442/4/9452/4 "To User_Vcc" Operating Mode Comments Settings The SMDS2+ main board To user_Vcc supplies V to the target External TB9442/4/ board (evaluation chip) and Target 9452/4 System the target system. SMDS2+ The SMDS2+ main board To user_Vcc supplies V...
Page 173 S3C9442/C9444/F9444/C9452/C9454/F9454 DEVELOPMENT TOOLS Table 16-3. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments Connector from External External Trigger Triggers Sources of the Application System You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions.
Page 174 DEVELOPMENT TOOLS S3C9442/C9444/F9444/C9452/C9454/F9454 J101 P1.0 P0.0/ADC0/INT0 P1.1 P0.1/ADC1/INT1 /P1.2 P0.2/ADC2 RESET T0/P2.0 P0.3/ADC3 P2.1 P0.4/ADC4 P2.2 P0.5/ADC5 P2.3 P0.6/ADC6/PWM P2.4 P0.7/ADC7 P2.5 P2.6/ADC8/CLO Figure 16-4. 20-Pin Connector for TB9442/4/9452/4 Target Board Target System J101 Part Name: AS20D Order Cods: SM6304 10 11 10 11 Figure 16-5.

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