1. Manuals
  2. Brands
  3. Samsung Manuals
  4. Microcontrollers
  5. S3C9444
  6. User manual

Samsung S3C9444 User Manual

8-bit cmos microcontrollers
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
USER'S MANUAL
S3C9444/F9444
8-Bit CMOS MICROCONTROLLERS
November, 2008
REV 1.10
Confidential Proprietary of Samsung Electronics Co., Ltd
Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved

Advertisement

Table of Contents
loading

Related Manuals for Samsung S3C9444

Summary of Contents for Samsung S3C9444

  • Page 1 USER’S MANUAL S3C9444/F9444 8-Bit CMOS MICROCONTROLLERS November, 2008 REV 1.10 Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved...
  • Page 2 Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
  • Page 3 NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea PRODUCT NAME: S3C9444/F9444 8-bit CMOS Microcontroller DOCUMENT NAME: S3C9444/F9444 User's Manual, Revision 1.10 DOCUMENT NUMBER: 21.10-S3-C9444/F9444 - 112008 EFFECTIVE DATE: November, 2008 REVISION HISTORY Revision No Description of Change...
  • Page 4 REVISION DESCRIPTIONS FOR REVISION 1.10 Chapter Subjects (Major changes comparing with last version) Chapter Name Page Internal RC item is removed. 12. Electrical data 12-5...
  • Page 5 Chapter 6 SAM88RCRI Instruction Set Chapter 1, "Product Overview," is a high-level introduction to the S3C9444/F9444 with a general product description, and detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," explains the S3C9444/F9444 program and data memory, internal register file, and mapped control registers, and explains how to address them.

  • Page 6: Table Of Contents

    Table of Contents Part I — Programming Model Chapter 1 Product Overview SAM88RCRI Product Family........................1-1 S3C9444 Microcontroller..........................1-1 MTP ................................1-1 Features ...............................1-2 Block Diagram ..............................1-3 Pin Assignments............................1-4 Pin Descriptions ............................1-5 Pin Circuits ..............................1-6 Chapter 2 Address Spaces Overview ..............................2-1 Program Memory (ROM)..........................2-2 Register Architecture............................2-5...
  • Page 7 Interrupt Pending Function Types......................5-2 Interrupt Priority............................5-2 Interrupt Source Service Sequence ....................... 5-3 Interrupt Service Routines........................5-3 Generating Interrupt Vector Addresses ....................5-3 S3C9444 Interrupt Structure ........................5-4 Chapter 6 SAM88RCRI Instruction Set Overview..............................6-1 Register Addressing..........................6-1 Addressing Modes ..........................6-1 Flags Register (FLAGS).........................
  • Page 8 Port 0 ..............................9-3 Port 1 ..............................9-7 Chapter 10 Basic Timer Module Overview............................10-1 Basic Timer (BT) ............................10-2 Basic Timer Control Register (BTCON)....................10-2 Basic Timer Function Description......................10-3 Timer 0 .................................10-7 Timer 0 Control Registers (T0CON) .......................10-7 Timer 0 Function Description........................10-8 S3C9444/F9444_UM_REV1.10 MICROCONTROLLER...
  • Page 9 Chapter 14 Overview..............................14-1 Operating Mode Characteristics ......................14-2 Chapter 15 Development Tools Overview..............................15-1 SHINE ..............................15-1 SAMA Assembler ........................... 15-1 SASM86 ..............................15-1 HEX2ROM.............................. 15-1 Target Boards ............................15-2 MTPs ..............................15-2 TB9444/9454 Target Board........................15-3 viii S3C9444/F9444_UM_REV1.10 MICROCONTROLLER...
  • Page 10 Indexed Addressing to Program or Data Memory with Short Offset ......8 Indexed Addressing to Program or Data Memory with Long Offset ......9 3-10 Direct Addressing for Load Instructions...............10 3-11 Direct Addressing for Call and Jump Instructions............11 3-12 Relative Addressing .....................12 3-13 Immediate Addressing ....................12 S3C9444/F9444_UM_REV1.10 MICROCONTROLLER...
  • Page 11 System Clock Control Register (CLKCON)..............2 System Clock Circuit Diagram ..................3 Reset Block Diagram....................2 Timing for S3C9444 after RESET ................2 Port Data Register Format ..................2 Port 0 Circuit Diagram ....................3 Port 0 Control Register (P0CONL, Low Byte) ............4 Port 0 Interrupt Pending Registers (P0PND) ..............
  • Page 12 8-SOP-225 Package Dimensions ................2 14-1 Pin Assignment Diagram (8-Pin Package) ..............1 15-1 SMDS Product Configuration (SMDS2+)..............2 15-2 TB9444/9454 Target Board Configuration..............3 15-3 DIP Switch for Smart Option ..................5 15-4 20-Pin Connector for TB9444/9454 ................6 15-5 S3C9444/F9444/C9454/F9454 Probe Adapter for 20-DIP Package......6 S3C9444/F9444_UM_REV1.10 MICROCONTROLLER...
  • Page 13 Flag Notation Conventions ......................6-5 Instruction Set Symbols......................6-5 Instruction Notation Conventions ....................6-6 Opcode Quick Reference ......................6-7 Condition Codes ........................6-9 S3C9444/F9444 Register Values after RESET ..............8-2 S3C9444/F9444 Port Configuration Overview ................9-1 Port Data Register Summary....................9-2 14-1 Commonly Used Baud Rates Generated by 8-bit BRDATA ...........14-5 15-1 Absolute Maximum Ratings.....................15-2...
  • Page 14 Addressing the Common Working Register Area .................. 2-7 Standard Stack Operations Using PUSH and POP................2-9 Chapter 8: RESET and Power-Down Sample S3C9444 Initialization Routine....................8-6 Chapter 10: Basic Timer and Timer 0 Configuring the Basic Timer........................10-6 Configuring Timer 0 (Interval Mode) ...................... 10-11...
  • Page 15 Port 0 Control Register (Low Byte) ................4-9 P0PND Port 0 Interrupt Pending Register ................4-10 P0PND Port 0 Interrupt Pending Register ................4-10 P1CON Port 1 Control Register ....................4-11 STOPCON STOP Mode Control Register ..................4-12 System Mode Register....................4-12 T0CON TIMER 0 Control Register....................4-13 S3C9444/F9444_UM_REV1.10 MICROCONTROLLER...
  • Page 16 Rotate Left Through Carry ...................6-40 Rotate Right .........................6-41 Rotate Right Through Carry..................6-42 Subtract With Carry......................6-43 Set Carry Flag ......................6-44 Shift Right Arithmetic....................6-45 STOP Stop Operation ......................6-46 Subtract........................6-47 Test Complement Under Mask ..................6-48 Test Under Mask......................6-49 Logical Exclusive OR ....................6-50 S3C9444/F9444_UM_REV1.10 MICROCONTROLLER xvii...

  • Page 17: Chapter 1 Product Overview

    The S3C9444 has 2K/4K bytes of on-chip program ROM and 208 bytes of RAM. The S3C9444 is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring simple timer/counter, PWM.

  • Page 18: Features

    PRODUCT OVERVIEW S3C9444/F9444_UM_REV1.10 FEATURES Timer/Counters • SAM88RCRI CPU core • One 8-bit basic timer for watchdog function The SAM88RCRI core is low-end version of the One 8-bit timer/counter with time interval modes • • current SAM87 core. A/D Converter Memory Three analog input pins •...

  • Page 19: Block Diagram

    S3C9444/F9444_UM_REV1.10 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0/ADC0/INT0 Port 0 P0.1/ADC1/INT1 P0.2/ADC2 Port I/O and Interrupt Control Basic Timer P1.0 Timer 0 Port 1 P1.1 88RCRI P1.2 SAMRI CPU ADC0-ADC2 2 KB ROM 208 Byte 4 KB ROM Register file NOTE: P1.2 is used as input only...

  • Page 20: Pin Assignments

    PRODUCT OVERVIEW S3C9444/F9444_UM_REV1.10 PIN ASSIGNMENTS S3C9444 /P1.0 P0.0/ADC0/INT0 (8-DIP-300 /P1.1 P0.1/ADC1/INT1 8-SOP-225) RESET/P1.2 P0.2/ADC2 Figure 1-2. Pin Assignment Diagram (8-Pin DIP/SOP Package)

  • Page 21: Pin Descriptions

    S3C9444/F9444_UM_REV1.10 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C9444 Pin Descriptions Share In/Out Pin Description Name Type Pins Bit-programmable I/O port for Schmitt trigger input or ADC0–ADC2 push-pull output. Pull-up resistors are assignable by P0.0–P0.2 INT0/INT1 software. Port0 pins can also be used as A/D converter input, or external interrupt input.

  • Page 22: Pin Circuits

    PRODUCT OVERVIEW S3C9444/F9444_UM_REV1.10 PIN CIRCUITS P-channel N-channel Figure 1-4. Pin Circuit Type B Figure 1-3. Pin Circuit Type A Pull-up Enable Data Data Circuit Output Type C Output DIsable Disable Digital Input Figure 1-5. Pin Circuit Type C Figure 1-6. Pin Circuit Type D...
  • Page 23 S3C9444/F9444_UM_REV1.10 PRODUCT OVERVIEW Pull-up enable P0CONH P-CH Alternative Data Output P0.x N-CH Output Disable (Input Mode) Digital Input Interrupt Input Analog Input Enable Figure 1-7. Pin Circuit Type E-1...
  • Page 24 PRODUCT OVERVIEW S3C9444/F9444_UM_REV1.10 Open-drain Enable Pull-up enable P1.x Output Disable (Input Mode) Pull-down enable Digital Input Figure 1-8. Pin Circuit Type E-2...

  • Page 25: Chapter 2 Address Spaces

    Internal ROM mode, all of the 4-Kbyte internal program memory is used. The S3C9444 microcontroller has 208 general-purpose registers in its internal register file. Twenty-six bytes in the register file are mapped for system and peripheral control functions.

  • Page 26: Program Memory (Rom)

    S3C9444/F9444_UM_REV1.10 PROGRAM MEMORY (ROM) Normal Operating Mode The S3C9444 have 2-Kbytes (locations 0H–07FFH) or 4-Kbytes (locations 0H–0FFFH) of internal mask- programmable program memory. The first 2-bytes of the ROM (0000H–0001H) are interrupt vector address. Unused locations (0002H–00FFH except 3CH, 3DH, 3EH, 3FH) can be used as normal program memory.
  • Page 27 Smart option is the ROM option for starting condition of the chip. The ROM addresses used by smart option are from 003CH to 003FH. The S3C9444 only use 003EH, 003FH. Not used ROM address 003CH, 003DH should be initialized to be initialized to 00H. The default value of ROM is FFH (LVR enable, internal RC oscillator).
  • Page 28 PROGRAMMING TIP — Smart Option Setting << Interrupt Vector Address >> 0000H Vector 00H, INT_9444 ; S3C9444 has only one interrupt vector << Smart Option Setting >> 003CH ; 003CH, must be initialized to 0. ; 003DH, must be initialized to 0.

  • Page 29: Register Architecture

    ADDRESS SPACES REGISTER ARCHITECTURE The upper 64-bytes of the S3C9444's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 192-bytes of internal register file(00H–BFH) is called the general purpose register space. 234 registers in this space can be accessed; 208 are available for general- purpose use.
  • Page 30 ADDRESS SPACES S3C9444/F9444_UM_REV1.10 Peripheral Control Registers 64 Bytes of Common Area System Control Registers Working Registers General Purpose Register File 192 Bytes and Stack Area Figure 2-3. Internal Register File Organization...

  • Page 31: Common Working Register Area (C0H-Cfh)

    However, because the S3C9444 uses only page 0, you can use the common area for any internal data operation. The Register (R) addressing mode can be used to access this area Registers are addressed either as a single 8-bit register or as a paired 16-bit register.

  • Page 32: System Stack

    Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C9444, the SP must be initialized to an 8-bit value in the range 00H–0C0H.
  • Page 33 S3C9444/F9444_UM_REV1.10 ADDRESS SPACES PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SP ← C0H (Normally, the SP is set to C0H by the SP,#0C0H ;...

  • Page 34: Chapter 3 Addressing Modes

    S3C9444/F9444_UM_REV1.10 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.

  • Page 35: Register Addressing Mode (R)

    ADDRESSING MODES S3C9444/F9444_UM_REV1.10 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses an 16-byte working register space in the register file and an 4-bit register within that space (see Figure 3-2).

  • Page 36: Indirect Register Addressing Mode (Ir)

    S3C9444/F9444_UM_REV1.10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
  • Page 37 ADDRESSING MODES S3C9444/F9444_UM_REV1.10 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory REGISTER Example PAIR Instruction Point to References OPCODE register pair Program 16-bit Memory address points to program Program Memory memory Value used in OPERAND instruction Sample Instructions: CALL...
  • Page 38 S3C9444/F9444_UM_REV1.10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory 4-Bit 4 LSBs Working OPERAND Register Point to the OPCODE Address working register (1 of 16) Sample Instruction: Value used in OPERAND instruction R6, @R2 Figure 3-5. Indirect Working Register Addressing to Register File...
  • Page 39 ADDRESSING MODES S3C9444/F9444_UM_REV1.10 INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File Program Memory 4-Bit Working Register Address Register Next 3 Bits Point Pair OPCODE to working Example instruction register pair references either 16-Bit (1 of 8) program memory or address data memory...

  • Page 40: Indexed Addressing Mode (X)

    S3C9444/F9444_UM_REV1.10 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
  • Page 41 ADDRESSING MODES S3C9444/F9444_UM_REV1.10 INDEXED ADDRESSING MODE (Continued) Program Memory Register File XS (OFFSET) NEXT 3 Bits 4-Bit Working Register Register Address Point to working Pair OPCODE register pair 16-Bit (1 of 8) address added to offset LSB Selects 16-Bit 8-Bit...
  • Page 42 S3C9444/F9444_UM_REV1.10 ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Program Memory Register File (OFFSET) (OFFSET) Register NEXT 3 Bits 4-Bit Working Pair Register Address Point to working OPCODE 16-Bit register pair address (1 of 8) added to offset LSB Selects 16-Bit 8-Bit...

  • Page 43: Direct Address Mode (Da)

    ADDRESSING MODES S3C9444/F9444_UM_REV1.10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
  • Page 44 S3C9444/F9444_UM_REV1.10 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16-bit immediate address CALL DISPLAY Where DISPLAY is a 16-bit immediate address Figure 3-11.

  • Page 45: Relative Address Mode (Ra)

    ADDRESSING MODES S3C9444/F9444_UM_REV1.10 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.

  • Page 46: Chapter 4 Control Registers

    CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9444 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs.
  • Page 47 CONTROL REGISTERS S3C9444/F9444_UM_REV1.10 Table 4-1. System and Peripheral Control Registers Register name Mnemonic Address & Location RESET value (Bit) Address Timer 0 counter register T0CNT Timer 0 data register T0DATA Timer 0 control register T0CON – – – Location D3H is not mapped...
  • Page 48 S3C9444/F9444_UM_REV1.10 CONTROL REGISTERS Table 4-1. System and Peripheral Control Registers (Continued) Register Name Mnemonic Address Bit Values After RESET Port 0 data register Port 1 data register – – – – – Locations E2H–E6H are not mapped Port 0 control register...
  • Page 49 CONTROL REGISTERS S3C9444/F9444_UM_REV1.10 Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register address Register bit or bit function (hexadecimal) Full Register name mnemonic FLAGS - System Flags Register Bit Identifier RESET Value Read/Write...
  • Page 50 S3C9444/F9444_UM_REV1.10 CONTROL REGISTERS ADCON — A/D Converter Control Register Bit Identifier RESET Value Read/Write .7–.4 A/D Converter Input Pin Selection Bits ADC0 (P0.0) ADC1 (P0.1) ADC2 (P0.2) connected with GND internally connected with GND internally connected with GND internally connected with GND internally...
  • Page 51 CONTROL REGISTERS S3C9444/F9444_UM_REV1.10 BTCON — Basic Timer Control Register Bit Identifier RESET Value Read/Write .7–.4 Watchdog Timer Function Enable Bit Disable watchdog timer function Others Enable watchdog timer function .3–.2 Basic Timer Input Clock Selection Code /4096 /1024 /128 Invalid setting...
  • Page 52 Oscillator IRQ Wake-up Function Enable Bit Enable IRQ for main system oscillator wake-up function Disable IRQ for main system oscillator wake-up function .6–.5 Not used for S3C9444 .4–.3 Divided by Selection Bits for CPU Clock frequency Divide by 16 (f...
  • Page 53 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1") Overflow Flag (V) Operation result is ≤ + 127 or _ – 128 Operation result is > + 127 or < – 128 .3–.0 Not used for S3C9444...
  • Page 54 P0CONL — Port 0 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7–.6 Not used for the S3C9444 .5–.4 Port 0, P0.2/ADC2 Configuration Bits Schmitt trigger input Schmitt trigger input; pull-up enable Push-pull output A/D converter input (ADC2); Schmitt trigger input off .3–.2...
  • Page 55 Read/Write – – – – .7–.4 Not used for the S3C9444 Port 0.1/ADC1/INT1 Interrupt Enable Bit INT1 falling edge interrupt disable INT1 falling edge interrupt enable Port 0.1/ADC1/INT1 Interrupt Pending Bit No interrupt pending (when read) Pending bit clear (when write)
  • Page 56 Configure P1.1 as a n-channel open-drain output Port 1.0 N-channel open-drain Enable Bit Configure P1.0 as a push-pull output Configure P1.0 as a n-channel open-drain output .5–.4 Not used for S3C9444 .3–.2 Port 1, P1.1 Interrupt Pending Bits Schmitt trigger input; Schmitt trigger input; pull-up enable Output Schmitt trigger input;...
  • Page 57 .7–.3 Not used for S3C9444 Global Interrupt Enable Bit Disable all interrupts Enable all interrupt .1–.0 Page Select Bits Page 0 Page 1 (Not used for S3C9444) Page 2 (Not used for S3C9444) Page 3 (Not used for S3C9444) 4-12...
  • Page 58 – – – .7–.6 Timer 0 Input Clock Selection Bits /256 Not used for the S3C9444 .5–.4 Timer 0 Counter Clear Bit No effect Clear the timer 0 counter (when write) Not used for the S3C9444 Timer 0 Interrupt Enable Bit...

  • Page 59: Chapter 5 Interrupt Structure

    S3C9444/F9444_UM_REV1.10 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through an interrupt vector which is assigned in ROM address 0000H. Figure 5-1. S3F9-Series Interrupt Type INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source.

  • Page 60: Enable/Disable Interrupt Instructions (Ei, Di)

    INTERRUPT STRUCTURE S3C9444/F9444_UM_REV1.10 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The system mode register, SYM (DFH), is used to enable and disable interrupt processing. SYM.2 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.2. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing.

  • Page 61: Interrupt Source Service Sequence

    S3C9444/F9444_UM_REV1.10 INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal.

  • Page 62: S3C9444 Interrupt Structure

    INTERRUPT STRUCTURE S3C9444/F9444_UM_REV1.10 S3C9444 INTERRUPT STRUCTURE The S3C9444 microcontroller has three peripheral interrupt sources: — Timer 0 match — P0.0 external interrupt — P0.1 external interrupt Figure 5-3. S3C9444 Interrupt Structure...

  • Page 63: Chapter 6 Sam88Rcri Instruction Set

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET SAM88RCRI INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8-bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file.
  • Page 64 SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst,src Load dst,src Load program memory dst,src Load external data memory LDCD dst,src Load program memory and decrement LDED dst,src Load external data memory and decrement...
  • Page 65 S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL Call procedure IRET Interrupt return cc,dst Jump on condition code Jump unconditional cc,dst Jump relative on condition code Return Bit Manipulation Instructions dst,src...

  • Page 66: Flags Register (Flags)

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4–FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.

  • Page 67: Instruction Set Notation

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation – Value is unaffected Value is undefined Table 6-3.
  • Page 68 SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Working register pair RRp (p = 0, 2, 4, ..., 14) Register or working register reg or Rn (reg = 0–255, n = 0–15)
  • Page 69 S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IRR1 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1...
  • Page 70 SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – r1,R2 r2,R1 cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ IDLE ↓ ↓ ↓ ↓ ↓ ↓ STOP IRET ↓ ↓ ↓ ↓...

  • Page 71: Condition Codes

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal.

  • Page 72: Instruction Descriptions

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM87Ri instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...

  • Page 73: Adc Add With Carry

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Add with Carry dst,src dst ← dst + src + c Operation: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected.

  • Page 74: Add Add

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.

  • Page 75: And Logical And

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...

  • Page 76: Call Call Procedure

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 CALL — Call Procedure CALL ← Operation: SP – 1 ← ← SP –1 ← ← The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.

  • Page 77: Ccf Complement Carry Flag

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.

  • Page 78: Clr Clear

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Clear dst ← "0" Operation: The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: →...

  • Page 79: Com Complement

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise.

  • Page 80: Cp Compare

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Compare dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: Set if a "borrow"...

  • Page 81: Dec Decrement

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is – 128 (80H) and result value is + 127 (7FH);...

  • Page 82: Di Disable Interrupts

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Disable Interrupts SYM (2) ← 0 Operation: Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.

  • Page 83: Ei Enable Interrupts

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Enable Interrupts SYM (2) ← 1 Operation: An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.

  • Page 84: Idle Idle Operation

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected.

  • Page 85: Inc Increment

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. Flags: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise.
  • Page 86 SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 IRET — Interrupt Return IRET IRET FLAGS ← @SP Operation: SP ← SP + 1 PC ← @SP SP ← SP + 2 SYM(2) ← 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter.

  • Page 87: Jp Jump

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.

  • Page 88: Jr Jump Relative

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...

  • Page 89: Ld Load

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc...
  • Page 90 SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Load (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0,#10H R0 = 10H →...

  • Page 91: Ldc/Lde Load Memory

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes "Irr"...
  • Page 92 SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External...

  • Page 93: Ldcd/Lded Load Memory And Decrement

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location.

  • Page 94: Ldci/Ldei Load Memory And Increment

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 LDCI/LDEI — LOAD MEMORY AND INCREMENT LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location.

  • Page 95: Nop No Operation

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected.

  • Page 96: Or Logical Or

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...

  • Page 97: Pop Pop From Stack

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.

  • Page 98: Push Push To Stack

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 PUSH — Push To Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.

  • Page 99: Rcf Reset Carry Flag

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: Given: C = "1"...

  • Page 100: Ret Return

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.

  • Page 101: Rl Rotate Left

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.

  • Page 102: Rlc Rotate Left Through Carry

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Rotate Left Through Carry dst (0) ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...

  • Page 103: Rr Rotate Right

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

  • Page 104: Rrc Rotate Right Through Carry

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Rotate Right Through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...

  • Page 105: Sbc Subtract With Carry

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Subtract With Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.

  • Page 106: Scf Set Carry Flag

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. Flags: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex)

  • Page 107: Sra Shift Right Arithmetic

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.

  • Page 108: Stop Stop Operation

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input.

  • Page 109: Sub Subtract

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.

  • Page 110: Tcm Test Complement Under Mask

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Test Complement Under Mask dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).

  • Page 111: Tm Test Under Mask

    S3C9444/F9444_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.

  • Page 112: Xor Logical Exclusive Or

    SAM88RCRI INSTRUCTION SET S3C9444/F9444_UM_REV1.10 — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...
  • Page 113 = 5 V) depending on smart option. An external RC oscillation source provides a typical 4 MHz clock S3C9444/F9444. An internal capacitor supports the RC oscillator circuit. An external crystal or ceramic oscillation source provides a maximum 10 MHz clock. The and X pins connect the oscillation source to the on-chip clock circuit.
  • Page 114 Stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with RC-delay noise filter (for S3C9444/F9444, INT0-INT1). — In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The current CPU status is preserved, including stack pointer, program counter, and flags.
  • Page 115 S3C9444/F9444_UM_REV1.10 CLOCK CIRCUIT Figure 7-4. System Clock Circuit Diagram...
  • Page 116 RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This brings the S3C9444/F9444 into a known operating status. To ensure correct start-up, the user should take care that reset signal is not released before the V level is sufficient to allow MCU operation at the chosen frequency.
  • Page 117 RESET Internal RESET LVR RESET Watchdog RESET Figure 8-1. Reset Block Diagram Oscillation Stabilization wait time (6.55 ms/at 10 MHz) RESET Input Operation Mode Idle Mode Normal Mode or Power-Down Mode RESET Operation Figure 8-2. Timing for S3C9444 after RESET...
  • Page 118 External interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related external interrupts cannot be used). External interrupts INT0-INT1 in the S3C9444/F9444 interrupt structure meet this criteria. And, internal interrupt using external clock (timer, SIO etc) can be used to release stop mode also.
  • Page 119 RESET and POWER-DOWN S3C9444/F9444_UM_REV1.10 HARDWARE RESET VALUES Table 8-1 lists the values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation in normal operating mode. — A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
  • Page 120 S3C9444/F9444_UM_REV1.10 RESET and POWER-DOWN Table 8-1. Register Values After a Reset (Continued) Register Name Mnemonic Address Bit Values After RESET Port 0 data register Port 1 data register – – – – – Locations E2H–E6H are not mapped Port 0 control register...
  • Page 121 RESET and POWER-DOWN S3C9444/F9444_UM_REV1.10 PROGRAMMING TIP — Sample S3C9444 Initialization Routine ;--------------<< Interrupt Vector Address >> 0000H VECTOR 00H,INT_9444 ; S3C9444 has only one interrupt vector ;--------------<< Smart Option >> 003CH ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 0E7H ;...
  • Page 122 S3C9444/F9444_UM_REV1.10 RESET and POWER-DOWN PROGRAMMING TIP — Sample S3C9444 Initialization Routine (Continued) ;--------------<< Main loop >> MAIN: ; Start main loop BTCON,#02H ; Enable watchdog function ; Basic counter (BTCNT) clear • • CALL KEY_SCAN • • • CALL LED_DISPLAY •...
  • Page 123 RESET and POWER-DOWN S3C9444/F9444_UM_REV1.10 PROGRAMMING TIP — Sample S3C9444 Initialization Routine (Continued) ;--------------<< Interrupt Service Routines >> ; Interrupt enable bit and pending bit check INT_9444: T0CON,#00000010B ; Timer0 interrupt enable check Z,NEXT_CHK1 T0CON,#00000001B ; If timer0 interrupt was occurred, NZ,INT_TIMER0 ;...
  • Page 124 I/O PORTS OVERVIEW The S3C9444 has three I/O ports: with 18 pins total. You access these ports directly by writing or reading port data register addresses. All ports can be configured as LED drive. (High current output: typical 10 mA) Table 9-1.
  • Page 125 I/O PORTS S3C9444/F9444_UM_REV1.10 PORT DATA REGISTERS Table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics. Data registers for ports 0-2 have the structure shown in Figure 9-1. Table 9-2. Port Data Register Summary...
  • Page 126 S3C9444/F9444_UM_REV1.10 I/O PORTS PORT 0 Port 0 is a bit-programmable, general-purpose, I/O ports. You can select normal input or push-pull output mode. In addition, you can configure a pull-up resistor to individual pins using control register settings. It is designed for high-current functions such as LED direct drive. Part 0 pins can also be used as alternative functions (ADC input, external interrupt input).
  • Page 127 I/O PORTS S3C9444/F9444_UM_REV1.10 Port 0 Control Register (Low Byte) E7H, R/W [.7-.6] Not used for S3C9444 [.5-.4] Port 0, P0.2/ADC2 Configuration Bits 0 0 = Schmitt trigger input 0 1 = Schmitt trigger input; pull-up enable 1 0 = Push-pull output 1 1 = A/D converter input (ADC2);...
  • Page 128 S3C9444/F9444_UM_REV1.10 I/O PORTS Port 0 Interrupt Pending Register E8H, R/W [.7-.4] Not used for S3C9444 [.3] Port 0.1/ADC1/INT1, Interrupt Enable Bit 0 = INT1 falling edge interrupt disable 1 = INT1 falling edge interrupt enable [.2] Port 0.1/ADC1/INT1, Interrupt Pending Bit...
  • Page 129 I/O PORTS S3C9444/F9444_UM_REV1.10 PORT 1 Port 1, is a 3-bit I/O port with individually configurable pins. It can be used for general I/O port (Schmitt trigger input mode, push-pull output mode or n-channel open-drain output mode). In addition, you can configure a pull-up and pull-down resistor to individual pin using control register settings.
  • Page 130 [.6] Port 1.0 N-channel open-drain Enable Bit 0 = Configure P1.0 as a push-pull output 1 = Configure P1.0 as a N-channel open-drain output [.5-.4] Not used for S3C9444 [.3-.2] Port 1, P1.1 Configuration Bits 0 0 = Schmitt trigger input;...
  • Page 131 BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 MODULE OVERVIEW The S3C9444/F9444 has two default timers: an 8-bit basic timer, one 8-bit general-purpose timer/counter, called timer 0. Basic Timer (BT) You can use the basic timer (BT) in two different ways: —...
  • Page 132 BASIC TIMER and TIMER 0 S3C9444/F9444_UM_REV1.10 BASIC TIMER (BT) BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function.
  • Page 133 S3C9444/F9444_UM_REV1.10 BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than "1010B" (The "1010B" value disables the watchdog function). A reset clears BTCON to "00H", automatically enabling the watchdog timer function.
  • Page 134 BASIC TIMER and TIMER 0 S3C9444/F9444_UM_REV1.10 Oscillation Stabilization Time Normal Operating mode 0.8 V Reset Release Voltage RESET trst Internal Reset Release 0.8 V Oscillator Oscillator Stabilization Time BTCNT clock 10000B BTCNT value 00000B = (4096x16)/f WAIT Basic timer increment and...
  • Page 135 S3C9444/F9444_UM_REV1.10 BASIC TIMER and TIMER 0 Normal STOP Mode Oscillation Stabilization Time Normal Operating Operating Mode Mode STOP Instruction STOP Mode Execution Release Signal External Interrupt RESET STOP Release Signal Oscillator BTCNT clock 10000B BTCNT 00000B Value WAIT Basic Timer Increment...
  • Page 136 This example shows how to configure the basic timer to sample specification. 0000H VECTOR 00H,INT_9444 ; S3C9444 has only one interrupt vector ;--------------<< Smart Option >> 003CH ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 0E7H ;...
  • Page 137 11 = fosc 1 = No effect (when write) Timer 0 interrupt enable bit: 0 = Disable T0 interrupt Not used for S3C9444 1 = Enable T0 interrupt Not used for S3C9444 Timer 0 counter clear bit: 0 = No effect 1 = Clear the Timer 0 counter (when write) Figure 10-4.
  • Page 138 BASIC TIMER and TIMER 0 S3C9444/F9444_UM_REV1.10 TIMER 0 FUNCTION DESCRIPTION Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the Timer 0 reference data register, T0DATA. The match signal generates a Timer 0 match interrupt (T0INT, vector 00H) and then clears the counter.
  • Page 139 S3C9444/F9444_UM_REV1.10 BASIC TIMER and TIMER 0 Match Match Match Compare Value (T0DATA) Match Match Match Match Up Counter Value (T0CNT) Clear Clear Clear Count start T0CON.3 1 T0DATA Value change Counter Clear (T0CON.3) Interrupt Request (T0CON.0) T0 Match Output (P2.0) Figure 10-6.
  • Page 140 BASIC TIMER and TIMER 0 S3C9444/F9444_UM_REV1.10 Bit 1 RESET or STOP Basic Timer Control Register Bits 3, 2 (Write '1010xxxxB' to disable.) Data Bus Clear 1/4096 RESET 8-Bit Up Counter 1/1024 (BTCNT, Read-Only) 1/128 When BTCNT.4 is set after releasing from RESET or STOP mode, CPU clock starts.
  • Page 141 PROGRAMMING TIP1 – Configuring Timer 0 (Interval Mode) The following sample program sets Timer 0 to interval timer mode. 0000H VECTOR 00H,INT_9444 ; S3C9444 has only one interrupt vector 003CH ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 0E7H ;...
  • Page 142 BASIC TIMER and TIMER 0 S3C9444/F9444_UM_REV1.10 PROGRAMMING TIP1 – Configuring Timer 0 (Interval Mode) (Continued) LED_DISPLAY: • • • JOB: • • • ;--------------<< Interrupt Service Routines >> INT_9444: T0CON,#00000010B ; Interrupt enable check Z,NEXT_CHK1 T0CON,#00000001B ; If timer 0 interrupt was occurred, NZ,INT_TIMER0 ;...
  • Page 143 S3C9444/F9444_UM_REV1.10 A/D CONVERTER A/D CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the nine input channels to equivalent 10-bit digital values. The analog input level must lie between the V and V values.
  • Page 144 A/D CONVERTER S3C9444/F9444_UM_REV1.10 USING A/D PINS FOR STANDARD DIGITAL INPUT The ADC module's input pins are alternatively used as digital input in port 0.0, port 0.1 and port 0.2. A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address F7H. ADCON has four functions: —...
  • Page 145 S3C9444/F9444_UM_REV1.10 A/D CONVERTER INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range V to V Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step.
  • Page 146 A/D CONVERTER S3C9444/F9444_UM_REV1.10 ADC0N.0 50 ADC clock Conversion Start ADDATA Privious ADDATAH (8-bit) + ADDATAL (2-bit) Valid Value data Set-up time 40 clock 10 clock Figure 11-4. A/D Converter Timing Diagram CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up A/D conversion.
  • Page 147 S3C9444/F9444_UM_REV1.10 A/D CONVERTER Figure 11-5. Recommended A/D Converter Circuit for Highest Absolute Accuracy 11-5...
  • Page 148 A/D CONVERTER S3C9444/F9444_UM_REV1.10 PROGRAMMING TIP – Configuring A/D Converter 0000H VECTOR 00H,INT_9444 ; S3C9444 has only one interrupt vector 003CH ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 0E7H ; 003EH, enable LVR (2.3 V) ;...
  • Page 149 S3C9444/F9444_UM_REV1.10 A/D CONVERTER PROGRAMMING TIP – Configuring A/D Converter (Continued) CONV_LOOP: TM ADCON,#00001000B ; Check EOC flag Z,CONV_LOOP ; If EOC flag=0, jump to CONV_LOOP until EOC flag=1 R0,ADDATAH ; High 8 bits of conversion result are stored ; to ADDATAH register R1,ADDATAL ;...
  • Page 150 S3C9444/F9444_UM_REV1.10 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the following S3C9444/F9444 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Input Timing Measurement Points — Oscillator characteristics —...
  • Page 151 ELECTRICAL DATA S3C9444/F9444_UM_REV1.10 Table 12-1. Absolute Maximum Ratings ° = 25 Parameter Symbol Conditions Rating Unit Supply voltage – – 0.3 to + 6.5 Input voltage All ports – 0.3 to V + 0.3 – 0.3 to V + 0.3...
  • Page 152 S3C9444/F9444_UM_REV1.10 ELECTRICAL DATA Table 12-2. DC Electrical Characteristics ° ° = – 25 C to + 85 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit = 2.0 to 5.5 V 0.8 V Input high Ports 0, 1 and –...
  • Page 153 ELECTRICAL DATA S3C9444/F9444_UM_REV1.10 Table 12-3. AC Electrical Characteristics ° ° = – 25 C to + 85 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Interrupt input – – INT0, INT1 INTL = 5 V ± 10 %...
  • Page 154 S3C9444/F9444_UM_REV1.10 ELECTRICAL DATA Table 12-4. Oscillator Characteristics ° ° = – 25 C to + 85 Oscillator Clock Circuit Test Condition Unit = 4.5 to 5.5 V Main crystal or – ceramic = 2.7 to 4.5 V – = 2.0 to 2.7 V –...
  • Page 155 ELECTRICAL DATA S3C9444/F9444_UM_REV1.10 Figure 12-2. Operating Voltage Range Figure 12-3. Schmitt Trigger Input Characteristics Diagram 12-6...
  • Page 156 S3C9444/F9444_UM_REV1.10 ELECTRICAL DATA Table 12-6. Data Retention Supply Voltage in Stop Mode ° ° = – 25 C to + 85 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Data retention Stop mode – DDDR supply voltage Data retention Stop mode;...
  • Page 157 ELECTRICAL DATA S3C9444/F9444_UM_REV1.10 Table 12-7. A/D Converter Electrical Characteristics ° ° = – 25 C to + 85 C, V = 2.7 V to 5.5 V, V = 0 V) Parameter Symbol Test Conditions Unit ± 3 = 5.12 V Total accuracy –...
  • Page 158 S3C9444/F9444_UM_REV1.10 ELECTRICAL DATA Table 12-8. LVR Circuit Characteristics ° = 25 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Low voltage reset – – LVR hysteresis voltage – – Power supply voltage (note) rise time Power supply voltage...
  • Page 159 S3C9444/F9444_UM_REV1.10 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C9444 is available in a 8-pin DIP package (SAMSUNG 8-DIP-300A), a 8-pin SOP package (SAMSUNG 8- SOP-225). Package dimensions are shown in figure 13-1 and 13-2. Figure 13-1. 8-DIP-300 Package Dimensions 13-1...
  • Page 160 MECHANICAL DATA S3C9444/F9444_UM_REV1.10 8-SOP-225 + 0.10 0.15 - 0.05 5.13 MAX 4.92 0.20 0.10 MAX 1.27 (0.56) 0.41 ± 0.10 NOTE: Dimensions are in millimeters. Figure 13-2. 8-SOP-225 Package Dimensions 13-2...
  • Page 161 S3C9444/F9444 microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format. The S3F9444 is fully compatible with the S3C9444/F9444, in function, in D.C. electrical characteristics, and in pin configuration. Because of its simple programming requirements, the S3F9444 is ideal for use as an evaluation chip for the S3C9444/F9444.
  • Page 162 MTP enters into the writing mode). When 12.5 V is applied, MTP is in writing mode and when 5 V is applied, MTP is in reading mode. (Option) Logic power supply pin. Table 14-2. Comparison of S3F9444 and S3C9444 Features Characteristic S3F9444 S3C9444 Program Memory...
  • Page 163 SMDS2+, for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. SHINE Samsung Host Interface for in-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+.
  • Page 164 DEVELOPMENT TOOLS S3C9444/F9444_UM_REV1.10 TARGET BOARDS Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. MTPs Multi times programmable microcontrollers (MTPs) are under development for S3C9442/C9444 microcontroller. Figure 15-1. SMDS Product Configuration (SMDS2+)
  • Page 165 S3C9444/F9444_UM_REV1.10 DEVELOPMENT TOOLS TB9444/9454 TARGET BOARD The TB9444/9454 target board is used for the S3C9444/ C9454 microcontrollers. It is supported by the SMDS2+ development systems. Figure 15-2. TB9444/9454 Target Board Configuration 15-3...
  • Page 166 DEVELOPMENT TOOLS S3C9444/F9444_UM_REV1.10 Table 15-1. Power Selection Settings for TB9444/9454 "To User_Vcc" Operating Mode Comments Settings The SMDS2+ main board To user_Vcc External supplies V to the target TB9444/9454 Target System board (evaluation chip) and the target system. SMDS2+ The SMDS2+ main board...
  • Page 167 S3C9444/F9444_UM_REV1.10 DEVELOPMENT TOOLS Table 15-3. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments External Connector from Triggers External Trigger Sources of the Application System You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions.
  • Page 168 RESET /P1.2 P0.2/ADC2 T0/P2.0 P0.3/ADC3 P2.1 P0.4/ADC4 P2.2 P0.5/ADC5 P2.3 P0.6/ADC6/PWM P2.4 P0.7/ADC7 P2.5 P2.6/ADC8/CLO Figure 15-4. 20-Pin Connector for TB9444/9454 Target Board Target System J101 Part Name: AS20D Order Cods: SM6304 Figure 15-5. S3C9444/F9444/C9454/F9454 Probe Adapter for 20-DIP Package 15-6...

This manual is also suitable for:

S3f9444

Table of Contents