Reset And Power-Down - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
8

RESET AND POWER-DOWN

8.1 OVERVIEW OF SYSTEM RESET
Using the Smart option (3FH.7 in ROM), you can choose the Reset source as internal (LVR) or external.
S3F84B8 can be RESET in the following four ways:

External power-on-reset

External nRESET input pin pulled low

Digital watchdog peripheral time out

Low Voltage Reset (LVR)
During an external power-on reset, the voltage at V
some time. The nRESET signal is inputted through a Schmitt trigger circuit, where it is then synchronized to the
CPU clock. This brings the S3F84B8 into a known operating status. To ensure correct start-up, you should make
sure that the nRESET signal is not released before the V
the chosen frequency.
The nRESET pin must be held at low level for a minimum time interval, after the power supply comes within the
tolerance level. This allows time for internal CPU clock oscillation to stabilize.
When a reset occurs during normal operation (with both V
nRESET pin is forced to Low and the Reset operation starts. All system and peripheral control registers are then
set to their default hardware Reset values (see
The MCU provides a watchdog timer function to ensure recovery from any software malfunction. If watchdog timer
is not refreshed before an end-of-counter condition (overflow) is reached, the internal reset will be activated.
The on-chip Low Voltage Reset (LVR) features static Reset when supply voltage is below a reference value
(Typical voltages are 1.9V, 2.3V, 3.0V, 3.6V, and 3.9V). Owing to this feature, the external reset circuit can be
removed while keeping the application safe. As long as supply voltage is below reference value, there is an
internal and static RESET. The MCU can start only when supply voltage rises over reference value.
While calculating power consumption, remember that static current of LVR circuit should be added to the CPU
operating current in any operating modes such as Stop, Idle, and Normal Run mode.
is set to high level and the nRESET pin stays low level for
DD
level is sufficient. This allows the MCU to operate at
DD
and nRESET at high level), the signal at the
DD
Table 8-1, Table 8-2).
8-1
8 RESET AND POWER-DOWN