Adc — Add With Carry - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
6.3.1 ADC — ADD WITH CARRY
dst,src
ADC
dst  dst + src + c
Operation:
The source operand, along with the carry flag, is added to the destination operand. The sum is
stored in the destination. Contents of the source remain unaffected. Two's-complement addition is
performed. In multiple precision arithmetic, this instruction permits the carry from addition of low-
order operands into the addition of high-order operands.
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Flags:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result
is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if there is a carry from the most significant bit of the low-order four bits of the result;
cleared otherwise.
Format:
opc
opc
opc
Given R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register
Examples:
03H = 0AH:
ADC
ADC
ADC
ADC
ADC
In the first example, destination register R1 contains the value 10H, carry flag is set to "1", and
source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and
carry flag value ("1") to destination value 10H, leaving 14H in register R1.
dst | src
src dst
dst src

R1,R2

R1,@R2

01H,02H

01H,@02H

01H,#11H
Bytes
2
3
3
R1 = 14H, R2 = 03H
R1 = 1BH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 32H
6-13
6 INSTRUCTION SET
Cycles Opcode
(Hex)
4 12
6 13
6 14
6 15
6 16
Addr Mode
dst src
r r
r lr
R R
R IR
R IM