Tcm — Test Complement Under Mask - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
6.3.70 TCM — TEST COMPLEMENT UNDER MASK
dst,src
TCM
(NOT dst) AND src
Operation:
This instruction tests selected bits in destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of source operand (mask).
The TCM statement complements destination operand, which is then ANDed with source mask.
The zero (Z) flag can then be checked to determine the result. The destination and source
operands remain unaffected.
C: Unaffected.
Flags:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
opc
opc
opc
Given R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register
Examples:
02H = 23H:
TCM
TCM
TCM
TCM
TCM
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
contains the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination
register for a "1" value. Since the mask value corresponds to the test bit, the Z flag is set to logic
one and can be tested to determine the result of TCM operation.
dst | src
src dst
dst src
R0,R1
R0,@R1
00H,01H
00H,@01H
00H,#34
Bytes
2
3
3
R0 = 0C7H, R1 = 02H, Z = "1"
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "1"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "1"
Register 00H = 2BH, Z = "0"
6-82
6 INSTRUCTION SET
Cycles Opcode
(Hex)
4 62
6 63
6 64
6 65
6 66
Addr Mode
dst src
r r
r lr
R R
R IR
R IM