Tdcon — Timer D Control Register: E9H, Bank1 - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
4.1.43 TDCON — TIMER D CONTROL REGISTER: E9H, BANK1
Bit Identifier
RESET Value
Read/Write
.7–.6
5
.4
.3
.2
.1
.0
.7 .6
0 0
R/W R/W
Timer D Operating Mode Selection Bits
0 0 Interval mode
0 1 6-bit PWM mode (OVF interrupt can occur)
1 0 7-bit PWM mode (OVF interrupt can occur)
1 1 8-bit PWM mode (OVF interrupt can occur)
Timer D Counter Clear Bit
0 No effect
1 Clears the timer D counter (when write).
Timer D Start/Stop Bit
0 Stops Timer D.
1 Starts Timer D.
Timer D Match Interrupt Enable Bit
0 Disables interrupt.
1 Enables interrupt.
Timer D Overflow Interrupt Enable Bit
0 Disables interrupt.
1 Enables interrupt.
Timer D Match Interrupt Pending Bit
0 No interrupt is pending; clears pending bit (when write).
1 Interrupt is pending.
Timer D Overflow Interrupt pending Bit
0 No interrupt is pending; clears pending bit (when write).
1 Interrupt is pending.
.5 .4
0 0
R/W R/W R/W
4-40
4 CONTROL REGISTERS
.3 .2 .1
0 0 0
R/W R/W
.0
0
R/W