Resetid — Reset Source Indicating Register: F2H, Bank1 - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
4.1.33 RESETID — RESET SOURCE INDICATING REGISTER: F2H, BANK1
Bit Identifier
Read/Write
Addressing Mode
.7–.5
.4
.3
.2
.1
.0
LVR
WDT, or nReset pin
NOTE:
1. When LVR is disabled (Smart Option 3FH.7 = 0), RESETID.1 is invalid; when P0.2 is set as IO (Smart Option 3FH.2 = 0),
RESETID.4 is invalid.
2. To clear an indicating register, write "0" to indicating flag bit (writing "1" to reset indicating bits has no effect).
3. Once a LVR reset happens, RESETID.1 will be set and all the other bits will be cleared to "0" at the same time.
4. Once a WDT or nRESET pin reset happens, corresponding bit will be set, but leave all other indicating bits as unchanged.
.7 .6
– –
Register addressing mode only
Not used for S3F84B8.
nReset Pin Indicating Bit
0 Reset is not generated by nReset pin (when read).
1 Reset is generated by nReset pin (when read).
Not used for S3F84B8.
WDT Reset Indicating Bit
0 Reset is not generated by WDT (when read).
1 Reset is generated by WDT (when read).
LVR Reset Indicating Bit
0 Reset is not generated by LVR (when read).
1 Reset is generated by LVR (when read).
Not used for S3F84B8.
State of RESETID depends on the Reset Source
.7 .6
– –
– –
.5 .4 .3
– R/W –
.5 .4 .3
– 0 –
– –
(4)
4-32
4 CONTROL REGISTERS
.2 .1
R/W R/W
.2 .1
0 1
(4) (3)
.0
–
.0
–
–