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Samsung S3C84I8 User Manual

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USER'S MANUAL ERRATA
This document contains the corrections of errors,
typos and omissions in the following document.
Samsung 8-bit MCU S3C84I8/F84I8/C84I9/F84I9 User's Manual
Document Number: 21-S3-C84I8/F84I8/C84I9/F84I9-072006
Publication: July 2006

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  • Page 1 USER'S MANUAL ERRATA This document contains the corrections of errors, typos and omissions in the following document. Samsung 8-bit MCU S3C84I8/F84I8/C84I9/F84I9 User's Manual Document Number: 21-S3-C84I8/F84I8/C84I9/F84I9-072006 Publication: July 2006...
  • Page 2 S3C84I8/F84I8/C84I9/F84I9 ERRATA ERRATA (VER 0.0) Samsung 8-bit MCU S3C84I8/F84I8/C84I9/F84I9 User's Manual Document Number: 21-S3-C84I8/F84I8/C84I9/F84I9-072006 Publication: July 2006 Table 20-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin Name Pin No. Function P1.2...
  • Page 3 S3C84I8/F84I8/C84I9/F84I9 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1...
  • Page 4 Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
  • Page 5 Two order forms are included at the back of this manual to facilitate customer order for S3C84I8/F84I8/C84I9/F84I9 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.

  • Page 6: Table Of Contents

    Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8-Series Microcontrollers ........................1-1 S3C84I8/F84I8/C84I9/F84I9 Microcontroller ....................1-1 Features ................................1-2 Block Diagram ...............................1-3 Pin Assignment .............................1-4 Pin Assignment .............................1-5 Pin Descriptions ............................1-6 Pin Circuits ..............................1-9 Chapter 2 Address Spaces Overview................................2-1 Program Memory (ROM)..........................2-2...
  • Page 7 Overview ............................... 4-1 Chapter 5 Interrupt Structure Overview ............................... 5-1 Interrupt Types ............................. 5-2 S3C84I8/F84I8/C84I9/F84I9 Interrupt Structure.................. 5-4 Interrupt Vector Addresses ........................5-6 Enable/Disable Interrupt Instructions (EI, DI) ..................5-8 System-Level Interrupt Control Registers.................... 5-8 Interrupt Processing Control Points ..................... 5-9 Peripheral Interrupt Control Registers ....................
  • Page 8 I/O Ports Overview................................9-1 Port Data Registers ..........................9-2 Port 0 ..............................9-3 Port 1 ..............................9-5 Port 2 ..............................9-8 Port 3 ..............................9-12 Port 4 ..............................9-14 Chapter 10 Basic Timer Overview................................10-1 Basic Timer (BT)...........................10-1 basic Timer Control Register (BTCON)....................10-1 Basic Timer Function Description......................10-3 S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER...
  • Page 9 Overview ............................... 13-1 Function Description ............................. 13-1 PWM ..............................13-1 PWM Control Register (PWMCON)..................... 13-5 Chapter 14 Serial I/O Interface Overview ............................... 14-1 Programming Procedure........................14-1 Serial I/O Control Registers (SIOCON) ....................14-2 SIO Prescaler Register (SIOPS)......................14-3 viii S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER...
  • Page 10 LCD Controller/Driver Overview................................18-1 LCD Circuit Diagram ..........................18-2 LCD RAM Address Area ...........................18-3 LCD Mode Control Register (LMOD)......................18-4 LCD Port Control Register ........................18-5 LCD Voltage Dividing Resistors........................18-6 Common (COM) Signals...........................18-6 Segment (SEG) Signals..........................18-6 Chapter 19 Low Voltage Reset Overview................................19-1 S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER...
  • Page 11 Overview ............................... 22-1 Chapter 23 Development Tools Overview ............................... 23-1 SHINE ..............................23-1 SASM ..............................23-1 SAMA Assembler ..........................23-1 HEX2ROM ............................23-1 Target Boards ............................23-2 TB84I9 Target Board ........................... 23-3 Idle Led ..............................23-4 Stop Led............................... 23-4 S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER...
  • Page 12 Internal Register File Organization (S3C84I8/F84I8) ..........2-6 Register Page Pointer (PP) ..................2-7 Set 1, Set 2, Prime Area Register(S3C84I9/F84I9) ...........2-10 Set 1, Set 2, Prime Area Register (S3C84I8/F84I8) ..........2-11 8-Byte Working Register Areas (Slices) ..............2-12 Contiguous 16-Byte Working Register Block .............2-13 2-10 Non-Contiguous 16-Byte Working Register Block .............2-14...
  • Page 13 Title Page Number Number S3C8-Series Interrupt Types ..................5-3 S3C84I8/F84I8/C84I9/F84I9Interrupt Structure............5-5 ROM Vector Address Area ..................5-6 Interrupt Function Diagram ..................5-9 System Mode Register (SYM) ................... 5-11 Interrupt Mask Register (IMR) ................... 5-12 Interrupt Request Priority Groups ................5-13 Interrupt Priority Register (IPR) .................
  • Page 14 Internal Voltage Dividing Resistor Connection............18-6 18-7 LCD Signal Waveforms (1/8 Duty, 1/4 Bias) ..............18-7 18-8 LCD Signal Waveforms (1/4 Duty, 1/3 Bias) ..............18-8 18-9 LCD Signal Waveforms (1/3 Duty, 1/3 Bias) ..............18-9 19-1 Low Voltage Reset Circuit ..................19-2 S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER xiii...
  • Page 15 SMDS+ or SK-1000 Product Configuration ............... 23-2 23-2 S3F84I9/ S3F84I8/S3F84H5 Target Board Configuration......... 23-3 23-3 44-Pin Connector Pin Assignment for TB84I9............23-5 23-4 42-Pin Connector Pin Assignment for TB84I9............23-6 23-5 TB84I9 Adapter Cable for 44pin Connector Package ..........23-6 S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER...
  • Page 16 OPCODE Quick Reference ..................6-10 Condition Codes ......................6-12 S3C84I8/F84I8/84I9/F84I9 Set 1 Register Values After RESET .......8-2 S3C84I8/F84I8/84I9/F84I9 Set 1, Bank 0 Register Values After RESET ....8-3 S3C84I8/F84I8/84I9/F84I9 Set 1, Bank 1 Register Values After RESET ....8-4 S3C84I8/F84I8/84I9/F84I9 Port Configuration Overview...........9-1 Port Data Register Summary..................9-2 13-1 PWM Control and Data Registers ................13-2...
  • Page 17 21-11 A/D Converter Electrical Characteristics ..............21-12 21-12 LVR(Low Voltage Reset) Circuit Characteristics ............ 21-13 23-1 Power Selection Settings for TB84I9 ................. 23-4 23-2 Using Single Header Pins as the Input Path for External Trigger Sources ....23-4 S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER...
  • Page 18 Chapter 14: Serial I/O Interface SIO ................................14-5 Chapter 16: A/D Converter Configuring A/D Converter ..........................16-6 Chapter 17: Watch Timer Using the Watch Timer..........................17-4 Chapter 20: Embedded Flash Memory Interface Sector Erase..............................20-6 Programming ..............................20-8 Reading .................................20-10 Hard Lock Protection.............................20-11 S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER xvii...
  • Page 19 Timer A Control Register ....................4-40 TBCON Timer B Control Register ....................4-41 TINTPND Timer A, Timer 1 Interrupt Pending Register..............4-42 UARTCON UART Control Register ..................... 4-43 UARTPND UART Pending and Parity Control ..................4-45 WTCON Watch Timer Control Register ................... 4-46 S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER...
  • Page 20 Enable Interrupts ......................6-40 ENTER Enter ........................... 6-41 EXIT Exit..........................6-42 IDLE Idle Operation......................6-43 Increment ........................6-44 INCW Increment Word......................6-45 IRET Interrupt Return ......................6-46 Jump........................... 6-47 Jump Relative......................6-48 Load..........................6-49 Load..........................6-50 Load Bit ........................6-51 S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER...
  • Page 21 Subtract with Carry .....................6-77 Set Carry Flag......................6-78 Shift Right Arithmetic ....................6-79 SRP/SRP0/SRP1 Set Register Pointer....................6-80 STOP Stop Operation......................6-81 Subtract ........................6-82 SWAP Swap Nibbles......................6-83 Test Complement under Mask ...................6-84 Test under Mask ......................6-85 Wate for Interrupt......................6-86 Logical Exclusive OR....................6-87 xxii S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER...

  • Page 22: Chapter 1 Product Overview

    PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. The major CPU features are: — Efficient register-oriented architecture — Selectable CPU clock sources —...

  • Page 23: Features

    Memory • Real-time and interval time measurement. • 528-bytes internal register file(S3C84I9/F84I9) • Four frequency output to BUZ pin. • 272-bytes internal register file(S3C84I8/F84I8) • Clock generation for LCD. • 8Kbytes program memory (S3C84I8/F84I8) - Half-Flash LCD Controller/Driver (Optional) •...

  • Page 24: Block Diagram

    P2.0/TBPWM SAM8RC P4.0~P4.7/ P2.2/T1OUT0 P2.0/T1CK0 Port 4 SEG12~SEG19 16-Bit P2.1/T1CAP0 COM4~COM7 Timer/Counter P1.3/T1OUT1 10, 11 P1.4/T1CK1 P1.5/T1CAP1 ADC0~ADC7/ 8/32K-Byte 272/528-Byte P2.7/TxD P0.0~P0.3 UART P2.6/RxD P1.4~P1.5 P2.2~P2.3 COM0~COM4(COM8) LCD Driver/ SEG0~SEG19(SEG16) Controller P2.3/ P2.5/ P2.4/ P2.1/PWM Figure 1-1. S3C84I8/F84I8/C84I9/F84I9 Block Diagram...

  • Page 25: Pin Assignment

    P3.3/SEG7 INT2/TACAP/P1.2 P3.2/SEG6 S3C84I9/F84I9 INT3/T1OUT1/P1.3 P3.1/SEG5 S3C84I8/F84I8 P3.0/SEG4 P0 .3/C OM3 /A D3 Top View Xout P 0.2/C OM 2/AD2 (44-QFP) P 0.1/C OM 1/AD1 TEST P 0.0/C O M0/AD0 Xtin Avss Xtout Avref Figure 1-2. S3C84I8/F84I8/C84I9/F84I9Pin Assignment (44-pin QFP)
  • Page 26 S3C84I8/F84I8/C84I9/F84I9 PRODUCT OVERVIEW PIN ASSIGNMENT P4.1/SEG13 SEG14/P4.2 P4.0/SEG12 SEG15P4.3 P3.7/SEG11 SEG16/COM4/P4.4 P3.6/SEG10 SEG17/COM5/P4.5 P3.5/SEG9 COM6/SEG18/P4.6 P3.4/SEG8 COM7/SEG19/P4.7 P3.3/SEG7 INT0/TAOUT/P1.0 S3C84I9/F84I9 P3.2/SEG6 INT1/BUZ/TACK/P1.1 P3.1/SEG5 INT2/TACAP/P1.2 P3.0/SEG4 INT3/T1OUT1/P1.3 AD3/COM3/P0.3 AD2/COM2/P0.2 Top View AD1/COM1/P0.1 Xout (42-SDIP) AD0/COM0/P0.0 AVss TEST AVref XTin P2.7/SEG3/TxD XTout P2.6/SEG2/RxD...

  • Page 27: Pin Descriptions

    PRODUCT OVERVIEW S3C84I8/F84I8/C84I9/F84I9 PIN DESCRIPTIONS Table 1-1. S3C84I8/F84I8/C84I9/F84I9Pin Descriptions Circuit Share Name Type Description Type Number Pins P0.0–P0.3 Bit programmable port; input or output mode selected H-16 29-32 COM0/ADC0 by software; input or push-pull output. Software (25-28) COM1/ADC1 assignable pull-up resistor.
  • Page 28 S3C84I8/F84I8/C84I9/F84I9 PRODUCT OVERVIEW Table 1-1. S3C84I8/F84I8/C84I9/F84I9Pin Descriptions (Continued) Circuit Share Name Type Description Type Number Pins INT0–INT3 input pins for external interrupt. 7-10 P1.0–P1.3 Alternatively used as general-purpose digital (1-4) input/output port 1 ADC0–ADC7 Analog input pins for A/D converter module.
  • Page 29 PRODUCT OVERVIEW S3C84I8/F84I8/C84I9/F84I9 Table 1-1. S3C84I8/F84I8/C84I9/F84I9Pin Descriptions (Continued) Circuit Share Name Type Description Type Number Pins nRESET System reset pin 18(12) – TEST Pull-down resistor connected internally – 15(9) – – Power input pins – 11,12 – (5,6) Xin, Xout Main oscillator pins –...

  • Page 30: Pin Circuits

    S3C84I8/F84I8/C84I9/F84I9 PRODUCT OVERVIEW PIN CIRCUITS Pull-Up Resistor Schmitt Trigger Figure 1-4. Pin Circuit Type B (nRESET) P-Channel Data N-Channel Output Disable Figure 1-5. Pin Circuit Type C...
  • Page 31 PRODUCT OVERVIEW S3C84I8/F84I8/C84I9/F84I9 Pull-up Enable Data Pin Circuit Type C Output Disable Figure 1-6. Pin Circuit Type D Port Data Pull-up enable Alternative output Circuit Type C Output Disable Noise Ext.INT Filter Normal Input Figure 1-7. Pin Circuit Type D-5 (P1.0–P1.3)
  • Page 32 S3C84I8/F84I8/C84I9/F84I9 PRODUCT OVERVIEW Pull-up Resistor (Typical Value:50kΩ) Pull-up Enable Port Data Alternative Output In/Out Output DIsable Normal Input Analog Input Figure 1-8. Pin Circuit Type E (P2.2–P2.3) 1-11...
  • Page 33 PRODUCT OVERVIEW S3C84I8/F84I8/C84I9/F84I9 SEG/COM Output Disable Figure 1-9. Pin Circuit Type H-4 1-12...
  • Page 34 S3C84I8/F84I8/C84I9/F84I9 PRODUCT OVERVIEW Pull-up Open Drain EN P-CH Enable Data N-CH LCD Out EN SEG/COM Circuit Type H-4 Output Disable Input Figure 1-10. Pin Circuit Type H-14 (P4.4–P4.7) Open Drain EN Pull-up P-CH Enable Data N-CH LCD Out EN Circuit...
  • Page 35 PRODUCT OVERVIEW S3C84I8/F84I8/C84I9/F84I9 Pull-up Open Drain EN P-CH Enable Data N-CH LCD Out EN Circuit Type H-4 Output Disable Normal Input Figure 1-12. Pin Circuit Type H-17 (2.4–P2.7, P3.0–P3.7, P4.0–P4.3) 1-14...

  • Page 36: Chapter 2 Address Spaces

    A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3C84I9/F84I9 has an internal 32-Kbyte mask-programmable ROM / 32-Kbyte Flash ROM and 528-byte RAM. The S3C84I8/F84I8 has an internal 8-Kbyte mask-programmable ROM / 8-Kbyte Flash ROM and 272-byte RAM.

  • Page 37: Program Memory (Rom)

    Program memory (ROM) stores program codes or table data. The S3C84I9/F84I9 has 32Kbytes of internal mask programmable program memory and the S3C84I8/F84I8 has 8Kbytes of internal mask programmable program memory. The program memory address range is therefore 0H-7FFFH and 0H-1FFFH (see Figure 2-1).
  • Page 38 S3C84I8/F84I8/C84I9/F84I9 ADDRESS SPACES Smart Option Smart option is the ROM option for starting condition of the chip. The ROM addresses used by smart option are from 003CH to 003FH. The default value of ROM is FFH. ROM Address: 003CH Not used...

  • Page 39: Register Architecture

    20bytes are LCD data registers and 492 registers are for general-purpose use. In case of S3C84I8/F84I8 the total number of addressable 8-bit registers is 358. Of these 358 registers, 16 bytes are for CPU and system control registers, 50 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, 20bytes are LCD data registers and 256 registers are for general-purpose use.
  • Page 40 S3C84I8/F84I8/C84I9/F84I9 ADDRESS SPACES Set1 Page 1 Page 0 Bank 1 Bank 0 Set 2 System and Bytes Peripheral Control Registers General-Purpose (Register Addressing Mode) Data Registers (Indirect Register, Indexed Bytes Mode, and Stack Operations) System and Peripheral Control Registers (Register Addressing Mode)
  • Page 41 (Register Addressing Mode) Bytes Page 0 General Purpose Register (Register Addressing Mode) Prime Data Registers Bytes (All Addressing Modes) Page 2 LCD Display Registers NOTE: Page2's 00H~13H is used for LCD Display Registers Figure 2-4. Internal Register File Organization (S3C84I8/F84I8)

  • Page 42: Register Page Pointer (Pp)

    8-bit data bus) into as many as 2 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C84I8/F84I8/C84I9/F84I9 microcontroller, a paged register file expansion is implemented for data registers, and the register page pointer must be changed to address other pages.
  • Page 43 ADDRESS SPACES S3C84I8/F84I8/C84I9/F84I9 PROGRAMMING TIP — Using the Page Pointer for RAM clear (Page 0, Page 1) ; Destination ← 0, Source ← 0 PP,#00H #0C0H R0,#0FFH ; Page 0 RAM clear starts RAMCL0: DJNZ R0,RAMCL0 ; R0 = 00H ;...

  • Page 44: Register Set 1

    S3C84I8/F84I8/C84I9/F84I9 ADDRESS SPACES REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and bank 1.

  • Page 45: Prime Register Space

    ADDRESS SPACES S3C84I8/F84I8/C84I9/F84I9 PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3C84I9/F84I9's two 256-byte register pages (S3C84I89/F84I8's one 256-byte) is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset.
  • Page 46 S3C84I8/F84I8/C84I9/F84I9 ADDRESS SPACES Page 0 Set 1 Bank 0 Bank 1 Set 2 Prime CPU and system control Space General-purpose Page 2 LCD data Peripheral and I/O Register Area Figure 2-7. Set 1, Set 2, Prime Area Register (S3C84I8/F84I8) 2-11...

  • Page 47: Working Registers

    ADDRESS SPACES S3C84I8/F84I8/C84I9/F84I9 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices."...

  • Page 48: Using The Register Pointers

    S3C84I8/F84I8/C84I9/F84I9 ADDRESS SPACES USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, RP# point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
  • Page 49 ADDRESS SPACES S3C84I8/F84I8/C84I9/F84I9 F7H (R7) 8-Byte Slice F0H (R0) Register File 16-byte Non- Contains 32 contiguous 8-Byte Slices 1 1 1 1 0 X X X working register block 7H (R15) 0 0 0 0 0 X X X 8-Byte Slice 0H (R8) Figure 2-10.

  • Page 50: Register Addressing

    S3C84I8/F84I8/C84I9/F84I9 ADDRESS SPACES REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2.
  • Page 51 C0H-C7H and RP1 to locations C8H-CFH Registers (that is, to the common working register area). NOTE: In the S3C84I9/F84I9 microcontroller ,pages 0-2 are implemented and S3C84I8/F84I8 LCD Data microcontroller, page0-1 are inplemented. Registers Page0-2 contain all of the addressable registers in the internal register file.

  • Page 52: Common Working Register Area (C0H-Cfh)

    C0H-CFH. Page 2 LCD Data RP0 = 1 1 0 0 0 0 0 0 Register Area RP1 = 1 1 0 0 1 0 0 0 NOTE: S3C84I8/F84I8 doesn't have page 1 Figure 2-13. Common Working Register Area 2-17...

  • Page 53: 4-Bit Working Register Addressing

    ADDRESS SPACES S3C84I8/F84I8/C84I9/F84I9 PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Examples 1: 0C2H,40H ; Invalid addressing mode!
  • Page 54 S3C84I8/F84I8/C84I9/F84I9 ADDRESS SPACES Selects RP0 or RP1 Address OPCODE 4-bit address Register pointer provides three provides five low-order bits high-order bits Together they create an 8-bit register address Figure 2-14. 4-Bit Working Register Addressing 0 1 1 1 0 0 0 0...

  • Page 55: 8-Bit Working Register Addressing

    ADDRESS SPACES S3C84I8/F84I8/C84I9/F84I9 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B."...
  • Page 56 S3C84I8/F84I8/C84I9/F84I9 ADDRESS SPACES 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 Selects RP1 8-bit address Register form instruction 1 1 0 0 0 1 1 1 0 1 0 1 0 1 1...

  • Page 57: System And User Stack

    SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C84I8/F84I8/C84I9/F84I9 architecture supports stack operations in the internal register file.
  • Page 58 S3C84I8/F84I8/C84I9/F84I9 ADDRESS SPACES PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SPL ← FFH SPL,#0FFH ; (Normally, the SPL is set to 0FFH by the initialization ;...

  • Page 59: Chapter 3 Addressing Modes

    S3C84I8/F84I8/C84I9/F84I9 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.

  • Page 60: Register Addressing Mode (R)

    ADDRESSING MODES S3C84I8/F84I8/C84I9/F84I9 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).

  • Page 61: Indirect Register Addressing Mode (Ir)

    S3C84I8/F84I8/C84I9/F84I9 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
  • Page 62 ADDRESSING MODES S3C84I8/F84I8/C84I9/F84I9 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory REGISTER Example PAIR Instruction Points to References OPCODE Register Pair Program 16-Bit Memory Address Points to Program Program Memory Memory Sample Instructions: Value used in OPERAND Instruction CALL...
  • Page 63 S3C84I8/F84I8/C84I9/F84I9 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points Program Memory to start fo working register 4-bit block 3 LSBs Working Register Point to the OPCODE ADDRESS...
  • Page 64 ADDRESSING MODES S3C84I8/F84I8/C84I9/F84I9 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register 4-bit Working block Register Address Register Next 2-bit Point Pair OPCODE...

  • Page 65: Indexed Addressing Mode (X)

    S3C84I8/F84I8/C84I9/F84I9 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
  • Page 66 ADDRESSING MODES S3C84I8/F84I8/C84I9/F84I9 INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register block OFFSET NEXT 2 Bits 4-bit Working dst/src Register Register Address Point to Working...
  • Page 67 S3C84I8/F84I8/C84I9/F84I9 ADDRESSING MODES INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of Program Memory working register OFFSET block OFFSET NEXT 2 Bits 4-bit Working dst/src Register Register Address...

  • Page 68: Direct Address Mode (Da)

    ADDRESSING MODES S3C84I8/F84I8/C84I9/F84I9 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
  • Page 69 S3C84I8/F84I8/C84I9/F84I9 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16-bit immediate address CALL DISPLAY Where DISPLAY is a 16-bit immediate address Figure 3-11.

  • Page 70: Indirect Address Mode (Ia)

    ADDRESSING MODES S3C84I8/F84I8/C84I9/F84I9 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.

  • Page 71: Relative Address Mode (Ra)

    S3C84I8/F84I8/C84I9/F84I9 ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.

  • Page 72: Immediate Mode (Im)

    ADDRESSING MODES S3C84I8/F84I8/C84I9/F84I9 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.
  • Page 73 Part II of this manual. The locations and read/write characteristics of all mapped registers in the S3C84I8/F84I8/C84I9/F84I9 register file are listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, “RESET and Power-Down."...
  • Page 74 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 Table 4-2. Set 1, Bank 0 Registers Register Name Mnemonic Decimal Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register STOP control register STOPCON Port 0 control register...
  • Page 75 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER Table 4-3. Set 1, Bank 1 Registers Register Name Mnemonic Decimal Timer A, Timer 1 interrupt pending register TINTPND Timer A control register TACON Timer A data register TADATA Timer A counter register TACNT Timer 1(0) data register (High Byte)
  • Page 76 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 Name of individual Bit number(s) that is/are appended to the register name for bit addressing bit or related bits Register location in the internal Register address register file (hexadecimal) Register ID Register name FLAGS - System Flags Register...
  • Page 77 — A/D Converter Control Register Set 1, Bank0 Bit Identifier RESET Value Read/Write – Addressing Mode Register addressing mode only Not used for the S3C84I8/F84I8/C84I9/F84I9(must keep always 0) .6–.4 A/D Input Pin Selection Bits ADC0 ADC1 ADC2 ADC3 ADC4 ADC5...
  • Page 78 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 BTCON — Basic Timer Control Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.4 Watchdog Timer Function Disable Code (for System Reset) Disable watchdog timer function Other Vaules Enable watchdog timer function .3–.2...
  • Page 79 – – – – – Addressing Mode Register addressing mode only .7–.5 Not used for the S3C84I8/F84I8/C84I9/F84I9(must keep always 0) (note) .4–.3 CPU Clock (System Clock) Selection Bits fxx/16 fxx/8 fxx/2 fxx/1 (non-divided) Not used for the S3C84I8/F84I8/C84I9/F84I9(must keep always 0) .2–.0...
  • Page 80 INT Enable Bit During Sector Erase INT disable INT enable Sector Erase Fail Flag Sector Erase success Sector Erase fail Not used for the S3C84I8/F84I8/C84I9/F84I9 Flash Mode Start Bit (With Out Programming Mode & Reading Mode) Stop bit Start bit (auto cleared)
  • Page 81 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER FMSECH — Flash Memory Sector Register (High byte) Set 1, Bank1 Bit Identifier RESET Value Read/Write .7–.0 Flash Memory Sector address Bits You have to input High address of sector that’s accessed FMSECL — Flash Memory Sector Register (Low byte)
  • Page 82 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 FMUSR — Flash Memory User Programming Enable Register Set 1, Bank1 Bit Identifier RESET Value Read/Write .7–.0 Flash Memory User Programming Mode Selection Bits Others Disable user programming mode 10100101 Enable user programming mode 4-10...
  • Page 83 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER FLAGS — System Flags Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only Carry Flag (C) Operation does not generate a carry or underflow condition Operation generates a carry-out or underflow into high-order bit 7...
  • Page 84 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 — Interrupt Mask Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only Interrupt Level 7 (IRQ7) Enable Bit Disable (mask) Enable (un-mask) Interrupt Level 6 (IRQ6) Enable Bit Disable (mask) Enable (un-mask)
  • Page 85 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER — Instruction Pointer (High Byte) Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8).
  • Page 86 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 — Interrupt Priority Register Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C Group priority undefined B > C > A A >...
  • Page 87 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER — Interrupt Request Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only Interrupt Level 7 (IRQ7) Request Pending Bit Not pending Pending Interrupt Level 6 (IRQ6) Request Pending Bit Not pending Pending...
  • Page 88 RESET Value – – Read/Write – – Not used for S3C84I8/F84I8/C84I9/F84I9 COM Pins High Impedance Control Bit Normal COMs signal output COM pins are at high impedance Not used for S3C84I8/F84I8/C84I9/F84I9 LCD Display Control Bit Display off (cut off the LCD voltage dividing resistors) Normal display on .3-.2...
  • Page 89 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER LPOT — LCD Port Control Register Set 1, Bank1 Bit Identifier RESET Value – Read/Write – Not used for S3C84I8/F84I8/C84I9/F84I9 .6–.4 SEG4-SEG19 and COM0-COM3 Selection Bit SEG4-7 SEG8-11 SEG12-15 SEG16-19/ COM0-3 COM7-COM4 P3.0-P3.3 P3.4-P3.7 P4.0-P4.3 P4.4-P4.7 P0.0-P0.3...
  • Page 90 – – Addressing Mode Register addressing mode only .7–.4 Not used for the S3C84I8/F84I8/C84I9/F84I9 (must keep always 0) Main System Oscillator Control Bit Main System Oscillator RUN Main System Oscillator STOP Sub System Oscillator Control Bit Sub system oscillator RUN...
  • Page 91 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER P0CON — Port 0 Control Register (High Byte) Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P0.3/AD3/COM3 Configration Bits Input mode Input mode with pull-up Push-pull output mode Alternative function mode; AD3 input .5–.4...
  • Page 92 − − Read/Write Addressing Mode Register addressing mode only .7–.4 Not used for the S3C84I8/F84I8/C84I9/F84I9 (must keep always 0) .3–.2 P1.5/T1CAP1/AD6 Configration Bits Input mode (T1CAP1 input) Input mode with pull-up (T1CAP1 input) Push-pull output mode Alternative function mode: AD6 .1–.0...
  • Page 93 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER P1CONL — Port 1 Control Register (Low Byte) Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P1.3/T1OUT1/INT3 Configration Bits Input mode ; Interrupt input (INT3) Input mode with pull-up ; Interrupt input (INT3)
  • Page 94 – – Addressing Mode Register addressing mode only .7–.4 Not used for S3C84I8/F84I8/C84I9/F84I9 P1.3/INT3 Interrupt Pending Bit Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending P1.2/INT2 Interrupt Pending Bit Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending P1.1/INT1 Interrupt Pending Bit...
  • Page 95 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER P1INT — Port 1 Interrupt Enable Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P1.3's Interrupt Enable/Disble Selection Bit Interrupt Disable Interrupt Enable; Falling edge Interrupt Enable; Rising edge .5–.4 P1.2's Interrupt Enable/Disble Selection Bit...
  • Page 96 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 P2CONH — Port 2 Control Register (High Byte) Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P2.7/SEG3/TxD Configration Bits Input mode Alternative function mode: Not used Push-pull output mode Alternative function mode: TxD output .5-.4...
  • Page 97 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER P2CONL — Port 2 Control Register (Low Byte) Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7-.6 P2.3/AD7/SI Configration Bits Input mode ;SI input Alternative function mode: Not used Push-pull output mode Alternative function mode: AD7 .5-.4...
  • Page 98 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 P2PUR — Port 2 Pull-up Resistor Control Register Set 1, Bank0 Bit Identifier RESET Value Read/Write P2.7 Pull-up Resistor Enable/Disable Pull-up resistor disable Pull-up resistor enable P2.6 Pull-up Resistor Enable/Disable Pull-up resistor disable Pull-up resistor enable P2.5 Pull-up Resistor Enable/Disable...
  • Page 99 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER P3CONH — Port 3 Control Register (High Byte) Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P3.7/SEG11 Configration Bits Input mode Input mode with pull-up Push-pull output mode N-channel open-drain output .5–.4...
  • Page 100 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 P3CONL — Port 3 Control Register (Low Byte) Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P3.3/ SEG7 Configration Bits Input mode Input mode with pull-up Push-pull output mode N-channel open-drain output .5–.4...
  • Page 101 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER P4CONH — Port 4 Control Register (High Byte) Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P4.7/ COM7/SEG19 Configration Bits Input mode Input mode with pull-up Push-pull output mode N-channel open-drain output .5–.4...
  • Page 102 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 P4CONL — Port 4 Control Register (Low Byte) Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P4.3/ BUZ/SEG15 Configration Bits Input mode Input mode with pull-up Push-pull output mode N-channel open-drain output .5–.4...
  • Page 103 Don’t care NOTES: In the S3C84I8/F84I8 microcontroller, the internal register file is configured as two pages (Page 0, Page 2). The page 0 is used for the general-purpose register file and data register. In the S3C84I9/F84I9 microcontroller, the internal register file is configured as three pages (Page 0-2) The page 0 and page 1 are used for the general-purpose register file and data register .
  • Page 104 RESET Value – Read/Write – .7–.6 PWM Input Clock Selection Bits Not used for S3C84I8/F84I8/C84I9/F84I9 PWMDATA Reload Interval Selection Bit Reload from 10-bit up counter overflow Reload from 8-bit up counter overflow PWM Counter Clear Bit No effect Clear the PWM counter (when write)
  • Page 105 8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H–C7H. .2–.0 Not used for the S3C84I8/F84I8/C84I9/F84I9 — Register Pointer 1 Set 1 Bit Identifier RESET Value –...
  • Page 106 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 SIOCON — Serial I/O Module Control Registers Set 1, Bank1 Bit Identifier RESET Value Read/Write SIO Shift Clock Selection Bit Interval clock (P.S Clock) External clock (SCK) Data Direction Control Bit MSB-first mode LSB-first mode SIO Mode Selection Bit...
  • Page 107 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER SIOPS — SIO Prescaler Register Set 1, Bank1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.0 Baud rate = Input clock (fxx)/[(SIOPS + 1) ×4] or SCK input clock — Stack Pointer (High Byte)
  • Page 108 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 STOPCON — Stop Control Register Set 1, Bank0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instruction NOTE: Before execute the STOP instruction, You must set this STPCON register as “10100101b”.
  • Page 109 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER — System Mode Register Set 1 Bit Identifier RESET Value Read/Write – – – Addressing Mode Register addressing mode only .7–.5 Not used, But you must keep always 0 .4–.2 Fast Interrupt Level Selection Bits IRQ0 IRQ1...
  • Page 110 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 T1CON0 — Timer 1(0) Control Register Set 1, Bank1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.5 Timer 1(0) Input Clock Selection Bits fxx/1024 fxx/256 fxx/64 fxx/8 External clock falling edge External clock rising edge Counter stop .4–.3...
  • Page 111 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER T1CON1 — Timer 1(1) Control Register Set 1, Bank1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.5 Timer 1(1) Input Clock Selection Bits fxx/1024 fxx/256 fxx/64 fxx/8 External clock falling edge External clock rising edge Counter stop .4–.3...
  • Page 112 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 TACON — Timer A Control Register Set 1, Bank1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 Timer A Input Clock Selection Bits fxx/1024 fxx/256 fxx/64 External clock (TACK) .5–.4 Timer A Operating Mode Selection Bits...
  • Page 113 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER TBCON — Timer B Control Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 Timer B Input Clock Selection Bits fxx/4 fxx/8 fxx/64 fxx/256 .5–.4 Timer B Interrupt Time Selection Bits...
  • Page 114 – – Addressing Mode Register addressing mode only .7–.6 Not used for the S3C84I8/F84I8/C84I9/F84I9 (must keep always 0) Timer 1(1) Overflow Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending Timer 1(1) Match/Capture Interrupt Pending Bit...
  • Page 115 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER UARTCON — UART Control Register Set 1, Bank0 Bit Identifier RESET Value Read/Write .7–.6 Operating mode and baud rate selection bits Mode 0: Shift Register [fxx/(16 × (16bit BRDATA + 1))] Mode 1: 8-bit UART [fxx/(16 × (16bit BRDATA + 1))] Mode 2: 9-bit UART [fxx/(16 ×...
  • Page 116 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 UARTCON — UART Control Register (Continued) Set 1, Bank0 Bit Identifier RESET Value Read/Write Receive Interrupt Enable Bit Disable receive interrupt Enable receive interrupt Transmit Interrupt Enable Bit Disable transmit interrupt Enable transmit Interrupt NOTES: In mode 2, if the MCE (UARTCON.5) bit is set to "1", then the receive interrupt will not be activated if the received data bit is "0".
  • Page 117 S3C84I8/F84I8/C84I9/F84I9 CONTROL REGISTER UARTPND — UART Pending and Parity Control Set 1, Bank0 Bit Identifier RESET Value Read/Write – – – – .7–.6 Not used for the S3F84I5/F84I9 (must keep always 0) UART Parity Enable/Disable (PEN) Disable Enable UART Receive Parity Error (RPE)
  • Page 118 CONTROL REGISTERS S3C84I8/F84I8/C84I9/F84I9 WTCON — Watch Timer Control Register Set 1, Bank1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only Watch Timer Clock Selection Bit Main system clock divided by 256 (fxx/256) Sub system clock (fxt) Watch Timer Interrupt Enable Bit...
  • Page 119 (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to device. The S3C84I8/F84I8/C84I9/F84I9 interrupt structure recognizes eight interrupt levels. The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just identifiers for the interrupt levels that are recognized by the CPU.
  • Page 120 One level (IRQn) + one vector (V ) + multiple sources (S – S Type 3: One level (IRQn) + multiple vectors (V – V ) + multiple sources (S – S – S In the S3C84I8/F84I8/C84I9/F84I9microcontroller, two interrupt types are implemented.
  • Page 121 Type 3: IRQn S n + 1 S n + 2 S n + m NOTES: The number of Sn and Vn value is expandable In the S3C84I8/F84I8/84I9/F84I9 implementation, interrupt types 1 and 3 are used. Figure 5-1. S3C8-Series Interrupt Types...
  • Page 122 S3C84I8/F84I8/C84I9/F84I9 S3C84I8/F84I8/C84I9/F84I9 INTERRUPT STRUCTURE The S3C84I8/F84I8/C84I9/F84I9 microcontroller supports sixteen interrupt sources. All of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device- specific interrupt structure, as shown in Figure 5-2.
  • Page 123 DEH within the level IRQ5 the priorities within each level are set at the factory. 2. External interrupts are triggered by a rising or falling edge, depending on the corresponding control register setting. Figure 5-2. S3C84I8/F84I8/C84I9/F84I9Interrupt Structure...
  • Page 124 INTERRUPT STRUCTURE S3C84I8/F84I8/C84I9/F84I9 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C84I8/F84I8/C84I9/F84I9 interrupt structure are stored in the vector address area of the internal 8-Kbyte ROM, 0H–1FFFH(S3C84I8/F84I8) or 32-Kbyte ROM, 0H–7FFFH (S3C84I8/F84I9) (see Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
  • Page 125 S3C84I8/F84I8/C84I9/F84I9 INTERRUPT STRUCTURE Table 5-1. Interrupt Vectors Vector Address Request Reset/Clear Interrupt Source Decimal Interrupt Priority in Value Value Level Level √ 100H Basic timer (WDT) overflow nRESET √ UART transmit IRQ7 √ UART receive √ PWM overflow interrupt IRQ6 √...
  • Page 126 INTERRUPT STRUCTURE S3C84I8/F84I8/C84I9/F84I9 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities. NOTE The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure.
  • Page 127 S3C84I8/F84I8/C84I9/F84I9 INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are: — Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0) —...
  • Page 128 INTERRUPT STRUCTURE S3C84I8/F84I8/C84I9/F84I9 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers...
  • Page 129 S3C84I8/F84I8/C84I9/F84I9 INTERRUPT STRUCTURE SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing (see Figure 5-5). A reset clears SYM.0 to "0". The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register.
  • Page 130 INTERRUPT STRUCTURE S3C84I8/F84I8/C84I9/F84I9 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
  • Page 131 S3C84I8/F84I8/C84I9/F84I9 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
  • Page 132 INTERRUPT STRUCTURE S3C84I8/F84I8/C84I9/F84I9 Interrupt Priority Register (IPR) FFH ,Set 1, Bank 0, R/W Group priority: Group A 0 = IRQ0 > IRQ1 D7 D4 D1 1 = IRQ1 > IRQ0 0 = Undefined Group B 1 = B > C > A 0 = IRQ2 >...
  • Page 133 S3C84I8/F84I8/C84I9/F84I9 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on.
  • Page 134 "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software. In the S3C84I8/F84I8/C84I9/F84I9 interrupt structure, the timer B underflow interrupt (IRQ0) belongs to this category of interrupts in which pending condition is cleared automatically by hardware.
  • Page 135 S3C84I8/F84I8/C84I9/F84I9 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source.
  • Page 136 INTERRUPT STRUCTURE S3C84I8/F84I8/C84I9/F84I9 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack.
  • Page 137 S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files that are typical of most S3C8-series microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: —...
  • Page 138 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst,src Load dst,src Load bit dst,src Load external data memory dst,src Load program memory LDED dst,src Load external data memory and decrement LDCD dst,src Load program memory and decrement...
  • Page 139 S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions dst,src Add with carry dst,src dst,src Compare Decimal adjust Decrement DECW Decrement word dst,src Divide Increment INCW Increment word MULT dst,src Multiply dst,src Subtract with carry...
  • Page 140 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL Call procedure CPIJE dst,src Compare, increment and jump on equal...
  • Page 141 S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic SWAP Swap nibbles CPU Control Instructions Complement carry flag...
  • Page 142 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits which describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions. Two other flag bits, FLAGS.3 and FLAGS.2, are used for BCD arithmetic.
  • Page 143 S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET FLAG DESCRIPTIONS Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations have been performed, it contains the last value shifted out of the specified register.
  • Page 144 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation –...
  • Page 145 S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Bit (b) of working register Rn.b (n = 0–15, b = 0–7) Bit 0 (LSB) of working register Rn (n = 0–15)
  • Page 146 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 Table 6-5. OPCODE Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1.b, R2 BXOR r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb SRP/0/1 BTJR IRR1 r1,r2 r1,Ir2 R2,R1...
  • Page 147 S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET Table 6-5. OPCODE Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – DJNZ NEXT r1,R2 r2,R1 r1,RA cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ ↓ ENTER EXIT IDLE ↓ ↓ ↓ ↓ ↓ ↓ ↓...
  • Page 148 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal.
  • Page 149 S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This Chapter contains detailed information and programming examples for each instruction in the S3C8-series instruction set. Information is arranged in a consistent format for improved readability and for quick reference. The following information is included in each instruction description: —...

  • Page 150: Adc Add With Carry

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Add with Carry dst,src dst ← dst + src + c Operation: The source operand, along with the carry flag setting, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.

  • Page 151: Add Add

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.

  • Page 152: And Logical And

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation causes a "1" bit to be stored whenever the corresponding bits in the two operands are both logic ones;...

  • Page 153: Band Bit And

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET BAND — Bit AND dst,src.b BAND dst.b,src BAND dst(0) ← dst(0) AND src(b) Operation: dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or the source).

  • Page 154: Bcp Bit Compare

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Bit Compare dst,src.b dst(0) – src(b) Operation: The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.

  • Page 155: Bitc Bit Complement

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET BITC — Bit Complement dst.b BITC dst(b) ← NOT dst(b) Operation: This instruction complements the specified bit within the destination without affecting any other bit in the destination. C: Unaffected. Flags: Z: Set if the result is "0"; cleared otherwise.

  • Page 156: Bitr Bit Reset

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 BITR — Bit Reset dst.b BITR dst(b) ← 0 Operation: The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination. No flags are affected. Flags: Format: Bytes Cycles Opcode...

  • Page 157: Bits Bit Set

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET BITS — Bit Set dst.b BITS dst(b) ← 1 Operation: The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination. No flags are affected. Flags: Format: Bytes Cycles Opcode...
  • Page 158 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Bit OR dst,src.b dst.b,src dst(0) ← dst(0) OR src(b) Operation: dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination.

  • Page 159: Btjrf Bit Test, Jump Relative On False

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET BTJRF — Bit Test, Jump Relative on False dst,src.b BTJRF If src(b) is a "0", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter.

  • Page 160: Btjrt Bit Test, Jump Relative On True

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 BTJRT — Bit Test, Jump Relative on True dst,src.b BTJRT If src(b) is a "1", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC.

  • Page 161: Bxor Bit Xor

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET BXOR — Bit XOR dst,src.b BXOR dst.b,src BXOR dst(0) ← dst(0) XOR src(b) Operation: dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or the source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected.

  • Page 162: Call Call Procedure

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 CALL — Call Procedure CALL SP ← SP–1 Operation: @SP ← PCL SP ← SP–1 @SP ← PCH PC ← dst The contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction.

  • Page 163: Ccf Complement Carry Flag

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero. If C = "0", the value of the carry flag is changed to logic one.

  • Page 164: Clr Clear

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Clear dst ← "0" Operation: The destination location is cleared to "0". No flags are affected. Flags: Format: Bytes Cycles Opcode Addr Mode (Hex) Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: Examples: →...

  • Page 165: Com Complement

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement). All "1s" are changed to "0s", and vice-versa. C: Unaffected. Flags: Z: Set if the result is "0"; cleared otherwise.

  • Page 166: Cp Compare

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Compare dst,src dst–src Operation: The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. C: Set if a "borrow" occurred (src > dst); cleared otherwise.

  • Page 167: Cpije Compare, Increment, And Jump On Equal

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal dst,src,RA CPIJE If dst–src = "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter.

  • Page 168: Cpijne Compare, Increment, And Jump On Non-Equal

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 CPIJNE — Compare, Increment, and Jump on Non-Equal dst,src,RA CPIJNE If dst–src ≠ "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement...

  • Page 169: Da Decimal Adjust

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Decimal Adjust dst ← DA dst Operation: The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed (The operation is undefined if the destination operand is not the...
  • Page 170 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Decimal Adjust (Continued) Given: The working register R0 contains the value 15 (BCD), the working register R1 contains 27 Example: (BCD), and the address 27H contains 46 (BCD): C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH R1,R0 R1 ←...

  • Page 171: Dec Decrement

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Decrement dst ← dst–1 Operation: The contents of the destination operand are decremented by one. C: Unaffected. Flags: Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise.

  • Page 172: Decw Decrement Word

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 DECW — Decrement Word DECW dst ← dst – 1 Operation: The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one.

  • Page 173: Di Disable Interrupts

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Disable Interrupts SYM (0) ← 0 Operation: Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.

  • Page 174: Div Divide (Unsigned)

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Divide (Unsigned) dst,src dst ÷ src Operation: dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination.

  • Page 175: Djnz Decrement And Jump If Non-Zero

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero r,dst DJNZ r ← r – 1 Operation: If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.

  • Page 176: Ei Enable Interrupts

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Enable Interrupts SYM (0) ← 1 Operation: The EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have the highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when the EI instruction is executed.
  • Page 177 S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET ENTER — Enter ENTER SP ← SP – 2 Operation: @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer.
  • Page 178 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 EXIT — Exit EXIT IP ← @SP Operation: SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.

  • Page 179: Idle Idle Operation

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET IDLE — Idle Operation IDLE (See description) Operation: The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.

  • Page 180: Inc Increment

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. C: Unaffected. Flags: Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.

  • Page 181: Incw Increment Word

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET INCW — Increment Word INCW dst ← dst + 1 Operation: The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.

  • Page 182: Iret Interrupt Return

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 IRET — Interrupt Return IRET (Normal) RET (Fast) IRET FLAGS ← @SP PC ↔ IP Operation: SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine.

  • Page 183: Jp Jump

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true, otherwise, the instruction following the JP instruction is executed.

  • Page 184: Jr Jump Relative

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter, otherwise, the instruction following the JR instruction is executed.

  • Page 185: Ld Load

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. No flags are affected. Flags: Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc...
  • Page 186 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Load (Continued) Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, Examples: register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → LD R0,#10H R0 = 10H →...

  • Page 187: Ldb Load Bit

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Load Bit dst,src.b dst.b,src dst(0) ← src(b) Operation: dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected.
  • Page 188 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 LDC/LDE — Load Memory dst,src dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes "Irr"...

  • Page 189: Ldc/Lde Load Memory

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET LDC/LDE — Load Memory (Continued) LDC/LDE Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations Examples: 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: ;...
  • Page 190 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 LDCD/LDED — Load Memory and Decrement dst,src LDCD dst,src LDED dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
  • Page 191 S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET LDCI/LDEI — Load Memory and Increment dst,src LDCI dst,src LDEI dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
  • Page 192 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 LDCPD/LDEPD — Load Memory with Pre-Decrement dst,src LDCPD dst,src LDEPD rr ← rr – 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair and is first decremented.
  • Page 193 S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment dst,src LDCPI dst,src LDEPI rr ← rr + 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair and is first incremented.

  • Page 194: Ldw Load Word

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Load Word dst,src dst ← src Operation: The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. No flags are affected. Flags: Format: Bytes Cycles Opcode Addr Mode...

  • Page 195: Mult Multiply (Unsigned)

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET MULT — Multiply (Unsigned) dst,src MULT dst ← dst × src Operation: The 8-bit destination operand (the even numbered register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.
  • Page 196 INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 NEXT — Next NEXT PC ← @IP Operation: IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.

  • Page 197: Nop No Operation

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — No Operation No action is performed when the CPU executes this instruction. Typically, one or more NOPs are Operation: executed in sequence in order to affect a timing delay of variable duration. No flags are affected.

  • Page 198: Or Logical Or

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1", otherwise, a "0"...

  • Page 199: Pop Pop From Stack

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Pop from Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. No flags are affected.

  • Page 200: Popud Pop User Stack (Decrementing)

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 POPUD — Pop User Stack (Decrementing) dst,src POPUD dst ← src Operation: IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.

  • Page 201: Popui Pop User Stack (Incrementing)

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET POPUI — Pop User Stack (Incrementing) dst,src POPUI dst ← src Operation: IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.

  • Page 202: Push Push To Stack

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 PUSH — Push to Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.

  • Page 203: Pushud Push User Stack (Decrementing)

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) dst,src PUSHUD IR ← IR – 1 Operation: dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.

  • Page 204: Pushui Push User Stack (Incrementing)

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 PUSHUI — Push User Stack (Incrementing) dst,src PUSHUI IR ← IR + 1 Operation: dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.

  • Page 205: Rcf Reset Carry Flag

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Cleared to "0". Flags: No other flags are affected. Format: Bytes Cycles Opcode (Hex) Given: C = "1" or "0": Example: The instruction RCF clears the carry flag (C) to logic zero.

  • Page 206: Ret Return

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.

  • Page 207: Rl Rotate Left

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag, as shown in the figure below.

  • Page 208: Rlc Rotate Left Through Carry

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Rotate Left through Carry dst (0) ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C), and the initial value of the carry flag replaces bit zero.

  • Page 209: Rr Rotate Right

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

  • Page 210: Rrc Rotate Right Through Carry

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Rotate Right through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag, and the initial value of the carry flag replaces bit 7 (MSB).

  • Page 211: Sb0 Select Bank 0

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Select Bank 0 BANK ← 0 Operation: The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting the bank 0 register addressing in the set 1 area of the register file.

  • Page 212: Sb1 Select Bank 1

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Select Bank 1 BANK ← 1 Operation: The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting the bank 1 register addressing in the set 1 area of the register file.

  • Page 213: Sbc Subtract With Carry

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Subtract with Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.

  • Page 214: Scf Set Carry Flag

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. C: Set to "1". Flags: No other flags are affected. Format: Bytes Cycles Opcode (Hex) The statement SCF sets the carry flag to “1”.

  • Page 215: Sra Shift Right Arithmetic

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.

  • Page 216: Srp/Srp0/Srp1

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 SRP/SRP0/SRP1 — Set Register Pointer SRP0 SRP1 If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (3–7) Operation: If src (1) = 0 and src (0) = 1 then: RP1 (3–7) ←...

  • Page 217: Stop Stop Operation

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET STOP — Stop Operation STOP The STOP instruction stops the both the CPU clock and system clock and causes the Operation: microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.

  • Page 218: Sub Subtract

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.

  • Page 219: Swap Swap Nibbles

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET SWAP — Swap Nibbles SWAP dst (0 – 3) ↔ dst (4 – 7) Operation: The contents of the lower four bits and the upper four bits of the destination operand are swapped. C: Undefined. Flags: Z: Set if the result is "0"; cleared otherwise.

  • Page 220: Tcm Test Complement Under Mask

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Test Complement under Mask dst,src (NOT dst) AND src Operation: This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).

  • Page 221: Tm Test Under Mask

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Test under Mask dst,src dst AND src Operation: This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.

  • Page 222: Wfi Wate For Interrupt

    INSTRUCTION SET S3C84I8/F84I8/C84I9/F84I9 — Wate for Interrupt The CPU is effectively halted before an interrupt occurs, except that DMA transfers can still take Operation: place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt.

  • Page 223: Xor Logical Exclusive Or

    S3C84I8/F84I8/C84I9/F84I9 INSTRUCTION SET — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different.
  • Page 224 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the Main clock of S3C84I8/F84I8/C84I9/F84I9 by an external crystal can range from 1 MHz to 10 MHz. The maximum CPU clock frequency is 10 MHz. The X and X pins connect the external oscillator or clock source to the on-chip clock circuit.
  • Page 225 CLOCK CIRCUIT S3C84I8/F84I8/C84I9/F84I9 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset operation or an external interrupt (with RC delay noise filter).
  • Page 226 SCF84I9/F84I9 CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and has the following functions: — Oscillator frequency divide-by value After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.
  • Page 227 CLOCK CIRCUIT S3C84I8/F84I8/C84I9/F84I9 Oscillator Control Register (OSCCON) F2H, Set 1, Bank 0, R/W System clock selection bit: Not used (must keep always 0) 0 = Main oscillator select 1 = Subsystem oscillator select Not used (must keep always 0) Subsystem oscillator control bit:...
  • Page 228 RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C84I8/F84I8/84I9/F84I9 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance.
  • Page 229 — An "x" means that the bit value is undefined after a reset. — A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value. Table 8-1. S3C84I8/F84I8/84I9/F84I9 Set 1 Register values after RESET Address...
  • Page 230 RESET S3C84I8/F84I8/84I9/F84I9 and POWER-DOWN Table 8-2. S3C84I8/F84I8/84I9/F84I9 Set 1, Bank 0 Register values after RESET Address Bit values after Reset Register Name Mnemonic Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register...
  • Page 231 RESET and POWER-DOWN S3C84I8/F84I8/84I9/F84I9 Table 8-3. S3C84I8/F84I8/84I9/F84I9 Set 1, Bank 1 Register values after RESET Address Bit values after Reset Register Name Mnemonic TINTPND Timer A, 1 interrupt pending register TACON Timer A control register TADATA Timer A data register...
  • Page 232 External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller's current internal operating mode. The external interrupts in the S3C84I8/F84I8/84I9/F84I9 interrupt structure that can be used to release Stop mode are: —...
  • Page 233 RESET and POWER-DOWN S3C84I8/F84I8/84I9/F84I9 How to Enter into Stop Mode There are two steps to enter into Stop mode: 1. Handling STOPCON register to appropriate value (10100101B). 2. Writing Stop instruction (keep the order). IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active.
  • Page 234 I/O PORTS OVERVIEW The S3C84I8/F84I8/84I9/F84I9 microcontroller has five bit-programmable I/O ports, P0-P4. This gives a total of 34 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required.
  • Page 235 S3C84I8/F84I8/84I9/F84I9 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C84I8/F84I8/84I9/F84I9 I/O port data registers. Data registers for ports 0, 1, 2, 3 and 4 have the general format shown in Table 9-2.
  • Page 236 S3C84I8/F84I8/84I9/F84I9 I/O PORTS PORT 0 Port 0 is an 4-bit I/O port that you can use two ways: — General-purpose digital I/O — Alternative function: COM0~COM3, AD0~AD3 Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location E0H in set 1, bank 0.
  • Page 237 I/O PORTS S3C84I8/F84I8/84I9/F84I9 Port 0 Control Register, Low Byte (P0CON) E6H, Set1, Bank0, R/W, Reset value="00H" [.7-.6] P0.3/ADC3/COM3 Configuration Bits 0 0 = Input mode 0 1 = Input mode with pull-up 1 0 = Push-pull output mode 1 1 = Alternative function mode;AD3 input [.5-.4] P0.2/AD2/COM2 Configuration Bits...
  • Page 238 S3C84I8/F84I8/84I9/F84I9 I/O PORTS PORT 1 Port 1 is a 6-bit I/O port with individually configurable pins that you can use two ways: — General-purpose digital I/O — Alternative function: INT0~INT3, TAOUT, TACK, TACAP, T1OUT1,T1CK1,T1CAP1,AD5,AD6 Port 1 is accessed directly by writing or reading the port 1 data register, P1 at location E1H in set 1, bank 0.
  • Page 239 I/O PORTS S3C84I8/F84I8/84I9/F84I9 Port 1 Control Register, High Byte (P1CONH) E8H, Set1, Bank0, R/W, Reset value="00" [.7-.4] Not used (must keep always 0) [.3-.2] P1.5/T1CAP1/AD5 Configuration Bits 0 0 = Input mode; T1CAP1 input 0 1 = Input mode with pull-up; T1CAP1 input...
  • Page 240 S3C84I8/F84I8/84I9/F84I9 I/O PORTS Port 1 Interrupt Pending Register (P1INTPND) EAH, Set1, Bank0, R/W, Reset value="00H" [.7-.4] Not used for S3C84I9/F84I9 [.3] P1.3/INT3 Interrupt Pending bit 0 = Interrupt request is not pending,pending bit clear when write 0 1 = Interrupt request is pending [.2] P1.2/INT2 Interrupt Pending bit...
  • Page 241 I/O PORTS S3C84I8/F84I8/84I9/F84I9 Port 1 Interrupt Enable Register (P1INT) EBH, Set1, Bank0, R/W, Reset value="00H" [.7-.6] P1.3's Interrupt Enable/Disable Selection Bit 0X = Disable Interrupt 10 = Enable Interrupt; Falling Edge 11 = Enable Interrupt; Rising Edge [.5-.4] P1.2s Interrupt Enable/Disable Selection Bit 0X = Disable Interrupt 10 = Enable Interrupt;...
  • Page 242 S3C84I8/F84I8/84I9/F84I9 I/O PORTS Port 2 Control Register, High Byte (P2CONH) ECH, Set1, Bank0, R/W, Reset value="00" [.7-.6] P2.7/SEG3/TxD Configuration Bits 0 0 = Input mode 0 1 = Alternative function mode; Not used 1 0 = Push-pull output mode 1 1 = Alternative function mode; TxD output [.5-.4] P2.6/SEG2/RxD Configuration Bits...
  • Page 243 I/O PORTS S3C84I8/F84I8/84I9/F84I9 Port 2 Control Register, Low Byte (P2CONL) EDH, Set1, Bank0, R/W, Reset value="00" [.7-.6] P2.3/AD7/SI Configuration Bits 0 0 = Input mode; SI 0 1 = Alternative function mode; Not used 1 0 = Push-pull output mode 1 1 = Alternative function mode;...
  • Page 244 S3C84I8/F84I8/84I9/F84I9 I/O PORTS Port 2 Pull-up Control Register (P2PUR) FAH, Set1, Bank0, R/W, Reset value="00" [.7] P2.7/Pull-up Resistor Enable/Disable 0 = Pull-up resistor disable 1 = Pull-up resistor enable [.6] P2.6/Pull-up Resistor Enable/Disable 0 = Pull-up resistor disable 1 = Pull-up resistor enable [.5] P2.5/Pull-up Resistor Enable/Disable...
  • Page 245 I/O PORTS S3C84I8/F84I8/84I9/F84I9 PORT 3 Port 3 is an 8-bit I/O port that can be used for general-purpose digital I/O. The pins are accessed directly by writing or reading the port 3 data register, P3 at location E3H in set 1, bank 0. P3.0–P3.7 can serve as inputs,...
  • Page 246 S3C84I8/F84I8/84I9/F84I9 I/O PORTS Port 3 Control Register, Low Byte (P3CONL) EFH, Set1, Bank0, R/W, Reset value="00" [.7-.6] P3.3/SEG7 Configuration Bits 0 0 = Input mode 0 1 = Input mode with pull-up 1 0 = Push-pull output mode 1 1 = N-channel open-drain output [.5-.4] P3.2/SEG7 Configuration Bits...
  • Page 247 I/O PORTS S3C84I8/F84I8/84I9/F84I9 PORT 4 Port 4 is a 8-bit I/O port that you can use two ways: — General-purpose digital I/O — Alternative function: SEG12~SEG19, COM4~COM7 Port 4 is accessed directly by writing or reading the port 4 data register, P4 at location E4H in set 1, bank 0.
  • Page 248 S3C84I8/F84I8/84I9/F84I9 I/O PORTS Port 4 Control Register, Low Byte (P4CONL) F1H, Set1, Bank0, R/W, Reset value="00" [.7-.6] P4.3/BUZ/SEG15 Configuration Bits 0 0 = Input mode 0 1 = Input mode with pull-up 1 0 = Push-pull output mode 1 1 = N-channel open-drain output [.5-.4] P4.2/SEG14 Configuration Bits...
  • Page 249 S3C84I8/F84I8/84I9/F84I9 BASIC TIMER BASIC TIMER OVERVIEW BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.
  • Page 250 BASIC TIMER S3C84I8/F84I8/84I9/F84I9 Basic Timer Control Register (BTCON) D3H, Set 1, R/W Watchdog timer enable bit: Divider clear bit: 1010B = Disable watchdog function 0 = No effect Other value = Enable watchdog function 1 = Clear divider Basic timer counter clear bit:...
  • Page 251 S3C84I8/F84I8/84I9/F84I9 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function.
  • Page 252 BASIC TIMER S3C84I8/F84I8/84I9/F84I9 Bit 1 RESET or STOP Bits 3, 2 Basic Timer Control Register (Write '1010xxxxB' to disable) Data Bus Clear fxx/4096 fxx/1024 8-Bit Up Counter RESET (BTCNT, Read-Only) fxx/128 (note) Start the CPU Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
  • Page 253 S3C84I8/F84I8/84I9/F84I9 8-BIT TIMER A/B 8-BIT TIMER A/B 8-BIT TIMER A OVERVIEW The 8-bit timer A is an 8-bit general-purpose timer/counter. Timer A has three operating modes, you can select one of them using the appropriate TACON setting: — Interval timer mode (Toggle output at TAOUT pin) —...
  • Page 254 8-BIT TIMER A/B S3C84I8/F84I8/84I9/F84I9 FUNCTION DESCRIPTION Timer A Interrupts (IRQ1, Vectors C0H and C2H) The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/ capture interrupt (TAINT). TAOVF is interrupt level IRQ1, vector C2H. TAINT also belongs to interrupt level IRQ1, but is assigned the separate vector address, C0H.
  • Page 255 S3C84I8/F84I8/84I9/F84I9 8-BIT TIMER A/B TIMER A CONTROL REGISTER (TACON) You use the timer A control register, TACON, to: — Select the timer A operating mode (interval timer, capture mode and PWM mode) — Select the timer A input clock frequency —...
  • Page 256 8-BIT TIMER A/B S3C84I8/F84I8/84I9/F84I9 BLOCK DIAGRAM TACON.2 TAOVF Overflow TACON.7-.6 Pending Data Bus TINTPND.1 TACON.0 f xx/1024 f xx/256 Clear 8-bit Up-Counter TACON.3 f xx/64 (Read Only) TACK TACON.1 Match TAINT 8-bit Comparator Pending TINTPND.0 TACAP Timer A Buffer TAOUT(TAPWM) TACON.5.-4...
  • Page 257 8-BIT TIMER B OVERVIEW The S3C84I8/F84I8/84I9/F84I9 micro-controller has an 8-bit timer called timer B. Timer B, which can be used to generate the carrier frequency of a remote controller signal. Also, it can be used as the programmable buzz signal generator that makes a sound with a various frequency from 200Hz to 20KHz.
  • Page 258 8-BIT TIMER A/B S3C84I8/F84I8/84I9/F84I9 TIMER B CONTROL REGISTER (TBCON) Timer B Control Register (TBCON) D0H, Set 1, Bank 0, R/W Timer B input clock selection bit: Timer B output flip-flop 00 = fxx/4 control bit: 01 = fxx/8 0 = T-FF is low...
  • Page 259 S3C84I8/F84I8/84I9/F84I9 8-BIT TIMER A/B TIMER B PULSE WIDTH CALCULATIONS HIGH To generate the above repeated waveform consisted of low period time, t , and high period time, t HIGH When T-FF = 0, = (TBDATAL + 1) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock.
  • Page 260 8-BIT TIMER A/B S3C84I8/F84I8/84I9/F84I9 Timer B Clock T-FF = '0' High TBDATAL = 01-FFH TBDATAH = 00H T-FF = '0' TBDATAL = 00H TBDATAH = 01-FFH T-FF = '0' TBDATAL = 00H TBDATAH = 00H T-FF = '1' High TBDATAL = 00H...
  • Page 261 S3C84I8/F84I8/84I9/F84I9 8-BIT TIMER A/B PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P2.0 This example sets Timer B to the repeat mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are: 8.795 µ...
  • Page 262 8-BIT TIMER A/B S3C84I8/F84I8/84I9/F84I9 PROGRAMMING TIP — To generate a one pulse signal through P2.0 This example sets Timer B to the one shot mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 40µs width pulse. The program parameters are: 40 µs...
  • Page 263 S3C84I8/F84I8/84I9/F84I9 8-BIT TIMER A/B PROGRAMMING TIP — Using the Timer A 0000h VECTOR 0C0h,TAMC_INT VECTOR 0C2h,TAOV_INT 0100h INITIAL: ; Disable Global/Fast interrupt → SYM SYM,#00h IMR,#00000010b ; Enable IRQ1 interrupt SPH,#00000000b ; Set stack area SPL,#00000000b BTCON,#10100011b ; Disable watch-dog P1CONL,#0ABH ;...
  • Page 264 8-BIT TIMER A/B S3C84I8/F84I8/84I9/F84I9 PROGRAMMING TIP — Using the Timer B 0000h VECTOR 0BEh,TBUN_INT 0100h INITIAL: SYM,#00h ; Disable Global/Fast interrupt IMR,#00000001b ; Enable IRQ0 interrupt SPH,#00000000b ; Set stack area SPL,#00000000b BTCON,#10100011b ; Disable Watch-dog P2CONL,#03H ; Enable TBPWM output...
  • Page 265 16-BIT TIMER 1(0,1) 16-BIT TIMER 1(0,1) OVERVIEW The S3C84I8/F84I8/84I9/F84I9 has two 16-bit timer/counters. The 16-bit timer 1(0,1) is an 16-bit general-purpose timer/counter. Timer 1(0,1) has three operating modes, one of which you select using the appropriate T1CON0, T1CON1 setting is —...
  • Page 266 16-BIT TIMER 1(0,1) S3C84I8/F84I8/84I9/F84I9 FUNCTION DESCRIPTION Timer 1(0,1) Interrupts (IRQ2, Vectors C4H, C6H, C8H and CAH) The timer 1(0) module can generate two interrupts, the timer 1(0) overflow interrupt (T1OVF0), and the Timer 1(0) match/capture interrupt (T1INT0). T1OVF0 is interrupt level IRQ2, vector C6H. T1INT0 also belongs to interrupt level IRQ2, but is assigned the separate vector address, C4H.
  • Page 267 S3C84I8/F84I8/84I9/F84I9 16-BIT TIMER 1(0,1) PWM Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T1OUT0, T1OUT1 pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1(0,1) data registers.
  • Page 268 16-BIT TIMER 1(0,1) S3C84I8/F84I8/84I9/F84I9 Timer 1 Control Register (T1CON0) E8H, Set 1, Bank 1, R/W (T1CON1) E9H, Set 1, Bank 1, R/W Timer 1 clock source selection bit: Timer 1 overflow interrupt enable bit 000 = fxx/1024 0 = Disable overflow interrupt...
  • Page 269 S3C84I8/F84I8/84I9/F84I9 16-BIT TIMER 1(0,1) Timer A, Timer 1 Pending Register (TINTPND) E0H, Set 1, Bank 1, R/W Timer A match/capture Not used interrupt pending bit (must keep always 0) 0 = No interrupt pending 1 = Interrrupt pending Timer A overflow...
  • Page 270 16-BIT TIMER 1(0,1) S3C84I8/F84I8/84I9/F84I9 BLOCK DIAGRAM T1CON.7-.5 T1CON.0 T1OVF Overflow f xx/1024 Pending Data Bus f xx/256 TINTPND f xx/64 fxx/8 fxx/1 Clear 16-bit Up-Counter T1CON.2 (Read Only) T1CK T1CON.1 Match T1INT 16-bit Comparator Pending TINTPND T1CAP 16-bit Timer Buffer T1OUT(T1PWM) T1CON.4-.3...
  • Page 271 S3C84I8/F84I8/84I9/F84I9 16-BIT TIMER 1(0,1) PROGRAMMING TIP — Using the Timer 1(0) 0000h VECTOR 0C4h,TIM1_INT 0100h INITIAL: SYM,#00h ; Disable Global/Fast interrupt IMR,#00001000b ; Enable IRQ2 interrupt SPH,#00000000b ; Set stack area SPL,#00000000b BTCON,#10100011b ; Disable Watch-dog T1CON0,#01000110b ; Enable interrupt ,fxx/64, Interval, ;...
  • Page 272 S3C84I8/F84I8/C84I9/F84I9 10-BIT PWM (PULSE WIDTH MODULATION 10-BIT PWM (PULSE WIDTH MODULATION) OVERVIEW This microcontroller has the 10-bit PWM circuit. The operation of all PWM circuit is controlled by a single control register, PWMCON. The PWM counter is a 10-bit incrementing counter. It is used by the 10-bit PWM circuits. To start the counter and enable the PWM circuits, you set PWMCON.2 to "1".
  • Page 273 10-BIT PWM (PULSE WIDTH MODULATION S3C84I8/F84I8/C84I9/F84I9 PWM Data and Extension Registers PWM (duty) data registers located in Set 1, Bank1 at address F3H-F4H, determine the output value generated by each 10-bit PWM circuit. To program the required PWM output, you load the appropriate initialization values into the 8-bit reference data register (PWMDATAH .7–.0) and the 2-bit extension data register (PWMDATAL .1–.0).
  • Page 274 S3C84I8/F84I8/C84I9/F84I9 10-BIT PWM (PULSE WIDTH MODULATION Table 13-2. PWM Output "stretch" Values for Extension Data Register (PWMDATAL .1–.0) PWMDATAL Bit (Bit1–Bit0) "Stretched" Cycle Number – 1, 3 1, 2, 3 PWM Data 100H 4 MHz Clock: 00000000B xxxxxx00B 250 ns...
  • Page 275 10-BIT PWM (PULSE WIDTH MODULATION S3C84I8/F84I8/C84I9/F84I9 PWM Clock: 4 MHz 500 ns 00000010B xxxxxx01B Basic PWMDATA waveform : 00001001B : xxxxxx01 B Extended waveform 4 MHz 750 ns Figure 13-2. 10-Bit Extended PWM Waveform 13-4...
  • Page 276 S3C84I8/F84I8/C84I9/F84I9 10-BIT PWM (PULSE WIDTH MODULATION PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is located at register address F5H. PWMCON is used the 10-bit PWM modules. Bit settings in the PWMCON register control the following functions: —...
  • Page 277 10-BIT PWM (PULSE WIDTH MODULATION S3C84I8/F84I8/C84I9/F84I9 PWMCON.6-.7 2-bit Extend bit 8-bit up counter (PWMDATAL) (PWMDATAH) 2-bit 8-bit Counter Counter PWMCON.2 "1" When REG > Count 8-bit Comparator P2.1/PWM "1" When REG = Count 8-bit Data Buffer Extension Control Logic Extension Data...
  • Page 278 S3C84I8/F84I8/C84I9/F84I9 10-BIT PWM (PULSE WIDTH MODULATION PROGRAMMING TIP — Programming the PWM Module to Sample Specifications ;--------------<< Interrupt Vector Address >> 0000H VECTOR 0DAH,INT_PWM ;--------------<< Initialize System and Peripherals >> 0100H RESET: ; disable interrupt BTCON,#10100011B ; Watchdog disable •...
  • Page 279 S3C84I8/F84I8/84I9/F84I9 SERIAL I/O INTERFACE SERIAL I/O INTERFACE OVERVIEW Serial I/O module, SIO can interface with various types of external devices that require serial data transfer. The components of each SIO function block are: — 8-bit control register (SIOCON) — Clock selection logic —...
  • Page 280 SERIAL I/O INTERFACE S3C84I8/F84I8/84I9/F84I9 SERIAL I/O CONTROL REGISTERS (SIOCON) The control registers for serial I/O interface, SIOCON, is located in Set1, Bank 1 at F2H. It has the control settings for SIO module. — Clock source selection (internal or external) for shift clock —...
  • Page 281 S3C84I8/F84I8/84I9/F84I9 SERIAL I/O INTERFACE SIO PRESCALER REGISTER (SIOPS) The control register for serial I/O interface module, SIOPS is located in Set 1, Bank 1 at F0H. The value stored in the SIO prescaler registers, SIOPS, lets you determine the SIO clock rate (baud rate)
  • Page 282 SERIAL I/O INTERFACE S3C84I8/F84I8/84I9/F84I9 Transmit IRQS Complete Set SIOCON.3 Figure 14-4. Serial I/O Timing in Transmit-Receive Mode (Tx at falling, SIOCON.4 = 0) Transmit IRQS Complete Set SIOCON.3 Figure 14-5. Serial I/O Timing in Transmit-Receive Mode (Tx at rising, SIOCON.4 = 1)
  • Page 283 S3C84I8/F84I8/84I9/F84I9 SERIAL I/O INTERFACE Shift Clock Data Input High Impedance Data Output Transmit IRQ5 Start Complete Figure 14-6. Serial I/O Timing in Receive-Only Mode PROGRAMMING TIP — SIO 0000H VECTOR 00H, INT_SIO 0100H INITIAL: SYM, #00H ; Global/Fast interrupt disable -> SYM BTCON, #10100010B ;...
  • Page 284 SERIAL I/O INTERFACE S3C84I8/F84I8/84I9/F84I9 PROGRAMMING TIP — SIO (Continued) MAIN: • • • CALL SUB_SIO ; Data transmit routine • • • MAIN SUB_SIO: SIODATA, TRANSBUF ; 1-byte transmission SIOCON, #00001000B ; Shift start (8-bit transmit) • • INT_SIO: SIOCON, #11111110 ;...
  • Page 285 S3C84I8/F84I8/84I9/F84I9 UART UART OVERVIEW The UART block has a full-duplex serial port with programmable operating modes: There is one synchronous mode and three UART (Universal Asynchronous Receiver/Transmitter) modes: — Shift Register I/O with baud rate of fxx/(16 × (16bit BRDATA+1)) —...
  • Page 286 UART S3C84I8/F84I8/84I9/F84I9 UART CONTROL REGISTER (UARTCON) The control register for the UART is called UARTCON at address F6H. It has the following control functions: — Operating mode and baud rate selection — Multiprocessor communication and interrupt control — Serial receive enable/disable control —...
  • Page 287 S3C84I8/F84I8/84I9/F84I9 UART UART Control Register (UARTCON) F6H, Set1, Bank 0, R/W, Reset Value: 00H Operating mode and Transmit interrupt enable bit: 0 = Disable baud rate selection bits 1 = Enable (see table below) Multiprocessor communication Received interrupt enable bit:...
  • Page 288 UART S3C84I8/F84I8/84I9/F84I9 UART INTERRUPT PENDING REGISTER (UARTPND) The UART interrupt pending register, UARTPND is located at address F4H. It contains the UART data transmit interrupt pending bit (UARTPND.0) and the receive interrupt pending bit (UARTPND.1). In mode 0 of the UART module, the receive interrupt pending flag UARTPND.1 is set to "1" when the 8th receive data bit has been shifted.
  • Page 289 S3C84I8/F84I8/84I9/F84I9 UART In mode 2 (9-bit UART data), by setting the parity enable bit (PEN) of UARTPND register to '1', the 9 data bit of transmit data will be an automatically generated parity bit. Also, the 9 data bit of the received data will be treated as a parity bit for checking the received data.
  • Page 290 UART S3C84I8/F84I8/84I9/F84I9 UART BAUD RATE DATA REGISTER (BRDATAH, BRDATAL) The value stored in the UART baud rate register, (BRDATAH, BRDATAL), lets you determine the UART clock rate (baud rate). UART Baud Rate Data Register (BRDATAH) EEH, Set1, Bank 1, R/W, Reset Value: FFH...
  • Page 291 S3C84I8/F84I8/84I9/F84I9 UART Table 15-1. Commonly Used Baud Rates Generated by 16bit BRDATA BRDATAH BRDATAL Baud Rate Oscillation Clock Decimal Decimal 230,400 Hz 11.0592 MHz 115,200 Hz 11.0592 MHz 57,600 Hz 11.0592 MHz 38,400 Hz 11.0592 MHz 19,200 Hz 11.0592 MHz 9,600 Hz 11.0592 MHz...
  • Page 292 UART S3C84I8/F84I8/84I9/F84I9 BLOCK DIAGRAM SAM88 Internal Data Bus 16 BIT UDATA BRDATA RxD (P2.6) Baud Rate Zero Detector Generator Write TxD (P2.7) Start Shift UDATA Control Tx Clock Send TxD (P2.7) Shift Clock Interrupt Rx Clock Receive Control Start Shift...
  • Page 293 S3C84I8/F84I8/84I9/F84I9 UART UART MODE 0 FUNCTION DESCRIPTION In mode 0, UART is input and output through the RxD (P2.6) pin and TxD (P2.7) pin outputs the shift clock. Data is transmitted or received in 8-bit units only. The LSB of the 8-bit value is transmitted (or received) first.
  • Page 294 UART S3C84I8/F84I8/84I9/F84I9 UART MODE 1 FUNCTION DESCRIPTION In mode 1, 10-bits are transmitted (through the TxD (P2.7) pin) or received (through the RxD (P2.6) pin). Each data frame has three components: — Start bit ("0") — 8 data bits (LSB first) —...
  • Page 295 S3C84I8/F84I8/84I9/F84I9 UART UART MODE 2 FUNCTION DESCRIPTION In mode 2, 11-bits are transmitted (through the TxD pin) or received (through the RxD pin). Each data frame has four components: — Start bit ("0") — 8 data bits (LSB first) — Programmable 9th data bit or parity bit —...
  • Page 296 UART S3C84I8/F84I8/84I9/F84I9 Clock Write to Shift Register (UARTDATA) Shift Stop Bit Start Bit TB8 or Parity bit RB8 or Parity bit Clock Stop Start Bit Bit Detect Sample Time Shift Figure 15-8. Timing Diagram for UART Mode 2 Operation...
  • Page 297 SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C9-series multiprocessor communication features let a "master" S3C84I8/F84I8/84I9/F84I9 send a multiple-frame serial message to a "slave" device in a multi- S3C84I8/F84I8/84I9/F84I9 configuration. It does this without interrupting other slave devices that may be on the same serial line.
  • Page 298 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications: 1. Set all S3C84I8/F84I8/84I9/F84I9 devices (masters and slaves) to UART mode 2 with parity disable. 2. Write the MCE bit of all the slave devices to "1". 3. The master device's transmission protocol is: —...
  • Page 299 S3C84I8/F84I8/84I9/F84I9 A/D CONVERTER A/D CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10-bit digital values. The analog input level must lie between the and AV values.
  • Page 300 A/D CONVERTER S3C84I8/F84I8/84I9/F84I9 A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located in set1, bank 0 at address F7H. ADCON is read-write addressable using 8-bit instructions only. But, the EOC bit, ADCON.3 is read only. ADCON has four functions: —...
  • Page 301 S3C84I8/F84I8/84I9/F84I9 A/D CONVERTER Conversion Data Register High Byte (ADDATAH) F8H, Set 1, Bank 0, Read only Conversion Data Register Low Byte (ADDATAL) F9H, Set 1, Bank 0, Read only Figure 16-2. A/D Converter Data Register (ADDATAH, ADDATAL) ADCON.4-.6 ADCON.2-.1 (Select one input pin of the assigned) To ADCON.3...
  • Page 302 A/D CONVERTER S3C84I8/F84I8/84I9/F84I9 INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range AV to AV Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step.
  • Page 303 S3C84I8/F84I8/84I9/F84I9 A/D CONVERTER INTERNAL A/D CONVERSION PROCEDURE 1. Analog input must remain between the voltage range of AV and AV 2. Configure P0.0–P0.3, P1.4–P1.5, P2.2–P2.3 for analog input before A/D conversions. To do this, you load the appropriate value to the P0CONL (for ADC0–ADC3), P1CONH (for ADC5–ADC6) and P1CONH (for ADC4,ADC7) registers.
  • Page 304 A/D CONVERTER S3C84I8/F84I8/84I9/F84I9 PROGRAMMING TIP — Configuring A/D Converter • • P0CON, #11111111B ; P0.0–P0.3 A/D Input MODE • • ADCON, #00000001B ; Channel ADC0, fxx/16, Conversion start ; A/D conversion end ? → EOC check AD0_CHK: ADCON, #00001000B Z, AD0_CHK ;...
  • Page 305 S3C84I8/F84I8/84I9/F84I9 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit1 and bit 6 of the watch timer mode register, WTCON.1and 6, to “1”. After the watch timer starts and elapses a time, the watch timer interrupt is automatically set to “1”, and interrupt requests...
  • Page 306 WATCH TIMER S3C84I8/F84I8/84I9/F84I9 WATCH TIMER CONTROL REGISTER (WTCON: R/W) WTCON.7 WTCON.6 WTCON.5 WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTCON.0 RESET "0" "0" "0" "0" "0" "0" "0" "0" Table 17-1. Watch Timer Control Register (WTCON): Set 1, Bank 1, F8H, R/W Bit Name...
  • Page 307 S3C84I8/F84I8/84I9/F84I9 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM BUZZER Output (BZOUT) WTCON.6 WTCON.5 WTCON.4 WTINT /64 (0.5 kHz) WTCON.3 /32 (1 kHz) /16 (2 kHz) /8 (4 kHz) WTCON.2 Enable/Disable Selector WTCON.1 WTCON.0 Circuit Frequency Clock WTCON.7 Dividing Selector 1 Hz...
  • Page 308 WATCH TIMER S3C84I8/F84I8/84I9/F84I9 PROGRAMMING TIP — Using the Watch Timer 0000h VECTOR 0D6h,WT_INT 0100h INITIAL: SYM,#00h ; Disable Global/Fast interrupt IMR,#00010000b ; Enable IRQ3 interrupt SPH,#00000000b ; Set stack area SPL,#0FFh BTCON,#10100011b ; Disable Watch-dog WTCON,#11001110b ; 0.5 kHz buzzer, 1.955ms duration interrupt ;...
  • Page 309 S3C84I8/F84I8/84I9/F84I9 LCD CONTROLLER/DRIVER LCD CONTROLLER/DRIVER OVERVIEW The S3C84I8/F84I8/84I9/F84I9 microcontroller can directly drive an up-to-128-dot (16segments x 8 commons) LCD panel. Its LCD block has the following components: — LCD controller/driver — Display RAM for storing display data — 16 segment output pins (SEG0–SEG15) —...
  • Page 310 LCD CONTROLLER/DRIVER S3C84I8/F84I8/84I9/F84I9 LCD CIRCUIT DIAGRAM Port Latch SEG15/P4.3 Control Display (Page2) Selector SEG0/P2.4 LPOT COM7/SEG16/P4.4 Control Timing Controller selector COM4/SEG19/P4.7 COM3/P0.0 Port Control Latch COM0/P0.3 LMOD Voltage Control Figure 18-2. LCD Circuit Diagram 18-2...
  • Page 311 S3C84I8/F84I8/84I9/F84I9 LCD CONTROLLER/DRIVER LCD RAM ADDRESS AREA RAM addresses of page 2 are used as LCD data memory. It is Read-only memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.
  • Page 312 LCD CONTROLLER/DRIVER S3C84I8/F84I8/84I9/F84I9 LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in SET 1, BANK 1, at address F6H, and is read/write addressable using register addressing mode. It has the following control functions. — LCD duty and bias selection —...
  • Page 313 S3C84I8/F84I8/84I9/F84I9 LCD CONTROLLER/DRIVER LCD PORT CONTROL REGISTER The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET, a LPOT values are cleared to "0". LCD Port Control Register F7H, SET1,B ANK1 R/W SEG0/P2.4 selection bit:...
  • Page 314 LCD CONTROLLER/DRIVER S3C84I8/F84I8/84I9/F84I9 LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias 1/4 Bias 1/3 Bias S3C84I9/F84I9 S3C84I9/F84I9 S3C84I9/F84I9 S3C84I8/F84I8 S3C84I8/F84I8 S3C84I8/F84I8 LMOD.4 LMOD.4 LMOD.4 Figure 18-6. Internal Voltage Dividing Resistor Connection COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
  • Page 315 S3C84I8/F84I8/84I9/F84I9 LCD CONTROLLER/DRIVER COM0 0 1 2 3 0 1 2 3 COM1 COM2 COM3 1 Frame COM4 COM5 COM6 COM7 COM0 COM1 COM2 SEG0 + 1/4V SEG0-COM0 - 1/4V Figure 18-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) 18-7...
  • Page 316 LCD CONTROLLER/DRIVER S3C84I8/F84I8/84I9/F84I9 SEG0 SEG1 COM0 1 Frame COM1 COM2 COM0 COM3 COM1 COM2 COM3 SEG0 SEG1 + 1/3 V COM0-SEG0 - 1/3 V Figure 18-8. LCD Signal Waveforms (1/4 Duty, 1/3 Bias) 18-8...
  • Page 317 S3C84I8/F84I8/84I9/F84I9 LCD CONTROLLER/DRIVER SEG1 SEG0 SEG2 COM0 1 Frame COM1 COM0 COM2 COM1 COM2 SEG0 SEG1 + 1/3 V COM0-SEG0 - 1/3 V Figure 18-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias) 18-9...
  • Page 318 (overflow) is reached, the internal reset will be activated. The S3C84I8/F84I8/84I9/F84I9 has a built-in low voltage reset circuit that allows detection of power voltage drop of external V input level to prevent a MCU from malfunctioning in an unstable MCU power level. This voltage detector works for the reset operation of MCU.
  • Page 319 LOW VOLTAGE RESET S3C84I8/F84I8/84I9/F84I9 Watchdog RESET nRESET Internal System Longger than 1us nRESET When the V level is lower than 2.8V Comparator Longger than 1us NOTES: 1. The target of voltage detection level is 2.8 V at VDD = 5 V 2.
  • Page 320 S3C84I8/F84I8/84I9/F84I9 EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F84I8/84I9 has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by ‘LDC’ instruction and the type of sector erase and a byte programmable flash, a user can program the data in a flash memory area any time you want.
  • Page 321 EMBEDDED FLASH MEMORY INTERFACE S3C84I8/F84I8/84I9/F84I9 VDD/VSS VDD/VSS 5 / 6 (44-pin) Logic power supply pin. 11/12 (42-pin) 20-2...
  • Page 322 S3C84I8/F84I8/84I9/F84I9 EMBEDDED FLASH MEMORY INTERFACE User Program Mode This mode supports sector erase and one protection modes. The S3F84I9 has the pumping circuit internally, therefore, 12.5V into Vpp (Test) pin is not needed. To program a flash memory in this mode several control registers will be used.
  • Page 323 EMBEDDED FLASH MEMORY INTERFACE S3C84I8/F84I8/84I9/F84I9 Flash Memory User Programming Enable Register After reset, the user-programming mode is disabled, because the value of FMUSR is “00000000B”. If necessary, you can use the user programming mode by setting the value of FMUSR is “10100101B”.
  • Page 324 S3C84I8/F84I8/84I9/F84I9 EMBEDDED FLASH MEMORY INTERFACE SECTOR ERASE User can erase a flash memory partially by using sector erase function only in User Program Mode. The only unit of flash memory to be erased and written in User Program Mode is called sector.
  • Page 325 EMBEDDED FLASH MEMORY INTERFACE S3C84I8/F84I8/84I9/F84I9 Flash Memory Sector Address Register (FMSECH) F9H, SET1, BANK1, R/W Flash Memory Sector Address Register Enable bit : You have to input High address of sector that's accessed Figure 20-4. Flash Memory Sector Address Register (FMSECH)
  • Page 326 S3C84I8/F84I8/84I9/F84I9 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING A flash memory is programmed in one byte unit after sector erase. And for programming safety's sake, must set FMSECH,FMSECL to flash memory sector value. The write operation of programming starts by ‘LDC’ instruction.
  • Page 327 EMBEDDED FLASH MEMORY INTERFACE S3C84I8/F84I8/84I9/F84I9 PROGRAMMING TIP — Programming Case1. 1BYTE Programming • • WR_BYTE: ; Write data “AAH” to flash memory address 4010H FMUSR,#0A5H ; User Program mode enable FMCON,#01010001B ; Programming mode enable FMSECH, #40H ; Set flash sector address FMSECL, #00H ;...
  • Page 328 S3C84I8/F84I8/84I9/F84I9 EMBEDDED FLASH MEMORY INTERFACE Case3. Programming to the flash memory space located in other sectors • • WR_INSECTOR2: R0,#40H R1,#40H FMUSR,#0A5H ; User Program mode enable FMCON,#01010001B ; Programming mode enable FMSECH,#01H ; Set sector address located in target address to write data FMSECL,#00H ;...
  • Page 329 EMBEDDED FLASH MEMORY INTERFACE S3C84I8/F84I8/84I9/F84I9 READING The read operation starts by ‘LDC’ instruction. The program procedure in User program Mode 1. Load a flash memory upper address into upper register of pair working register. 2. Load a flash memory lower address into lower register of pair working register.
  • Page 330 S3C84I8/F84I8/84I9/F84I9 EMBEDDED FLASH MEMORY INTERFACE HARD LOCK PROTECTION User can set Hard Lock Protection by write ‘0110’ in FMCON7-4. If this function is enabled, the user cannot write or erase the data in a flash memory area. This protection can be released by the chip erase execution (in the tool program mode or user program mode).
  • Page 331 S3C84I8/F84I8/84I9/F84I9 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C84I8/F84I8/84I9/F84I9 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D.C. electrical characteristics — A.C. electrical characteristics —...
  • Page 332 ELECTRICAL DATA S3C84I8/F84I8/84I9/F84I9 Table 21-1. Absolute Maximum Ratings ° = 25 Parameter Symbol Conditions Rating Unit Supply Voltage – – 0.3 to + 6.5 – 0.3 to V + 0.3 Input Voltage All input ports – 0.3 to V + 0.3...
  • Page 333 S3C84I8/F84I8/84I9/F84I9 ELECTRICAL DATA Table 21-3. D.C. Electrical Characteristics ° ° = – 25 C to + 85 C, 2.5V to 5.5 V) Parameter Symbol Conditions Typ. Unit Operation Voltage Fx = 0 – 8MHz, fxt = 32.8 kHz – LVR off Fx = 0 –...
  • Page 334 ELECTRICAL DATA S3C84I8/F84I8/84I9/F84I9 Table 21-3. D.C. Electrical Characteristics (Continued) ° ° = – 25 C to + 85 C, V = 2.5 V to 5.5 V) Parameter Symbol Conditions Typ. Unit = 25 °C LCD Voltage kΩ Dividing Resistor ⏐...
  • Page 335 S3C84I8/F84I8/84I9/F84I9 ELECTRICAL DATA Table 21-3. D.C. Electrical Characteristics (Concluded) ° ° = – 25 C to + 85 C, V = 2.5 V to 5.5 V) Parameter Symbol Conditions Typ. Unit = 4.5 V to 5.5 V – Supply Current...
  • Page 336 ELECTRICAL DATA S3C84I8/F84I8/84I9/F84I9 Table 21-4. A.C. Electrical Characteristics ° ° = – 25 C to + 85 C, 2.5V to 5.5 V) Parameter Symbol Conditions Typ. Unit Interrupt Input = 5 V – – INTH High, Low Width INTL (Ports 2) µs...
  • Page 337 S3C84I8/F84I8/84I9/F84I9 ELECTRICAL DATA Table 21-5. Main Oscillator Frequency (f OSC1 ° ° = – 25 C + 85 C, 2.5V to 5.5 V) Oscillator Clock Circuit Test Condition Typ. Unit = 2.5V to 5.5 V Main Crystal or – Ceramic = 2.5V to 5.5 V...
  • Page 338 ELECTRICAL DATA S3C84I8/F84I8/84I9/F84I9 OSC1 - 0.5 V 0.4 V Figure 21-3. Clock Timing Measurement at X Table 21-7. Sub Oscillator Frequency (f OSC2 ° ° = -25 C + 85 C, V = 2.5 to 5.5 V) Oscillator Clock Circuit Test Condition Typ.
  • Page 339 S3C84I8/F84I8/84I9/F84I9 ELECTRICAL DATA Table 21-9. Data Retention Supply Voltage in Stop Mode ° ° = – 25 C to + 85 C, 2.5V to 5.5 V) Parameter Symbol Conditions Unit Data Retention Stop mode – DDDR Supply Voltage Stop mode, V = 2.5 V...
  • Page 340 ELECTRICAL DATA S3C84I8/F84I8/84I9/F84I9 Oscillation Stabilization Time Idle Mode Stop Mode Data Retention Mode DDDR Normal Execution of Operating Mode STOP Instruction Interrupt 0.2 V WAIT NOTE: is the same as 4096 x 16 x BT clock WAIT Figure 21-5. Stop Mode (Main) Release Timing Initiated by Interrupts...
  • Page 341 S3C84I8/F84I8/84I9/F84I9 ELECTRICAL DATA Table 21-10. UART Timing Characteristics in Mode 0 (10 MHz) ° ° = – 25 C to + 85 C, 2.5V to 5.5 V, Load capacitance = 80 pF) Parameter Symbol Typ. Unit × 6 Serial port clock cycle time ×...
  • Page 342 ELECTRICAL DATA S3C84I8/F84I8/84I9/F84I9 Table 21-11. A/D Converter Electrical Characteristics ° ° = – 25 C to + 85 C, 2.5V to 5.5 V, V = 0 V) Parameter Symbol Test Conditions Typ. Unit Resolution – – ± 3 = 5.12 V Total accuracy –...
  • Page 343 S3C84I8/F84I8/84I9/F84I9 ELECTRICAL DATA Table 21-12. LVR(Low Voltage Reset) Circuit Characteristics ° = 25 Parameter Symbol Test Condition Unit LVR Voltage Level LVR is enabled by smart option ° = 25 Main Oscillator Frequency CPU Clock 10 MHz 8 MHz 1 MHz 2.5 V...
  • Page 344 ELECTRICAL DATA S3C84I8/F84I8/84I9/F84I9 S3C84I8/F84I8/ C84I9/F84I9 Figure 21-9. The Circuit Diagram to Improve EFT Characteristics NOTE: To improve EFT characteristics, we recommend using power capacitor near S3C84I8/F84I8/C84I9/F84I9 like Figure 21-9. 21-14...
  • Page 345 S3C84I8/F84I8/84I9/F84I9 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3F84I9/F84I9microcontrollers are available in a 42-SDIP-600, 44-QFP-1010 package. 0-15 42-SDIP-600 39.50 MAX ± 0.20 39.10 ± 0.10 0.50 1.78 ± 0.10 (1.77) 1.00 NOTE: Dimensions are in millimeters. Figure 22-1. 42-SDIP-600 Package Dimensions...
  • Page 346 MECHANICAL DATA S3C84I8/F84I8/84I9/F84I9 ± 0.30 13.20 ± 0.20 10.00 + 0.10 0.15 - 0.05 0.10 MAX 44-QFP-1010 + 0.10 0.35 - 0.05 0.05 MIN 0.80 (1.00) ± 0.10 2.05 2.30 MAX NOTE: Dimensions are in millimeters. Figure 22-2. 44-QFP-1010 Package Dimensions...
  • Page 347 SK-1000, for the S3C7-, S3C9-, and S3C8- microcontroller families. SMDS2+ is a newly improved version of SMDS2, and SK-1000 is supported by a third party tool vendor. Samsung also offers supporting software that includes, debugger, an assembler, and a program for setting options.
  • Page 348 Target boards are available for all the S3C8-series microcontrollers. All the required target system cables and adapters are included on the device-specific target board. TB84I9 is a specific target board for the S3C84I8/F84I8/84I9/F84I9 development. IBM-PC AT or Compatible Emulator (SMDS2+ or SK-1000)
  • Page 349 S3C84I8/F84I8/84I9/F84I9 DEVELOPMENT TOOLS TB84I9 TARGET BOARD The TB84I9 target board is used for the S3C84I9 and the S3F84I9 microcontroller. It is supported by the SMDS2+ or SK-1000 development system (In-Circuit Emulator).Figure 23-2. TB84I9 Target Board Configuration TB84I9/8/84H5 REV.X To User_V '200X.XX.XX...
  • Page 350 DEVELOPMENT TOOLS S3C84I8/F84I8/84I9/F84I9 Table 23-1. Power Selection Settings for TB84I9 To User_Vcc' Settings Operating Mode Comments SMDS2+ or SK-1000 supplies To User_V to the target board TB84I9 Target (evaluation chip) and the System target system. SMDS2+ or SK-1000 SMDS2+ or SK-1000 supplies...
  • Page 351 S3C84I8/F84I8/84I9/F84I9 DEVELOPMENT TOOLS J102 INT0/TAOUT/P1.0 P4.7/SEG19/COM7 INT1/BUZ/TACK/P1.1 P4.6/SEG18/COM6 INT2/TACAP/P1.2 P4.5/SEG17/COM5 P4.4/SEG16/COM4 INT3/T1OUT1/P1.3 P4.3/SEG15 P4.2/SEG14 P4.1/SEG13 P4.0/SEG12 TEST P3.7/SEG11 Xtin P3.6/SEG10 Xtout P3.5/SEG9 P3.4/SEG8 nRESET P3.3/SEG7 TBPWM/T1CK0/P2.0 P3.2/SEG6 T1CAP0/PWM/P2.1 T1OUT0/AD4/P2.2 P3.1/SEG5 AD5/T1CK1/P1.4 P3.0/SEG4 T1CAP1/AD6/P1.5 P0.3/COM3/AD3 P0.2/COM2/AD2 SI/AD7/P2.3 P0.1/COM1/AD1 SO/SEG0/P2.4 P0.0/COM0/AD0 SCK/SEG1/P2.5 Rx/SEG2/P2.6...
  • Page 352 DEVELOPMENT TOOLS S3C84I8/F84I8/84I9/F84I9 J102 SEG14/P4.2 P4.1/SEG13 SEG15P4.3 P4.0/SEG12 P3.7/SEG11 SEG16/COM4/P4.4 SEG17/COM5/P4.5 P3.6/SEG10 COM6/SEG18/P4.6 P3.5/SEG9 COM7/SEG19/P4.7 P3.4/SEG8 INT0/TAOUT/P1.0 P3.3/SEG7 INT1/BUZ/TACK/P1.1 P3.2/SEG6 INT2/TACAP/P1.2 P3.1/SEG5 INT3/T1OUT1/P1.3 P3.0/SEG4 AD3/COM3/P0.3 AD2/COM2/P0.2 Xout AD1/COM1/P0.1 AD0/COM0/P0.0 TEST AVss XTin AVref XTout P2.7/SEG3/TxD nRESET P2.6/SEG2/RxD TBPWM/T1CK0/P2.0 P2.5/SEG1/SCK PWM/T1CAP0/P2.1 P2.4/SEG0/SO...

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