Page 1 21-S3-P80C5/C80C5/C80C8 -052002 USER'S MANUAL S3P80C5/C80C5/C80C8 8-Bit CMOS Microcontrollers Revision 1...
Page 2 S3P80C5/C80C5/C80C8 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1...
Page 3 Samsung reserves the right to make changes in its applications intended to support or sustain life, or for products or product specifications with the intent to...
Page 4 Two order forms are included at the back of this manual to facilitate customer order for S3C80C5/C80C8 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative. S3P80C5/C80C5/C80C8...
Page 6: Table Of Contents
Table of Contents Part I — Programming Model Chapter 1 Product Overview Overview ..............................1-1 S3P80C5/C80C5/C80C8 Microcontroller ....................1-1 Features ..............................1-2 CPU ................................1-2 Block Diagram ............................1-3 Pin Assignments............................1-4 Pin Descriptions............................1-5 Pin Circuits ..............................1-6 Chapter 2 Address Spaces Overview ..............................2-1 Program Memory (ROM) .........................2-2 Register Architecture ..........................2-3...
Page 7 5-17 Chapter Instruction Set Overview .................6-1 ...................... Register Addressing ..................Addressing Modes ................... Flags Register (FLAGS) .................. Flag Descriptions..................... Instruction Set Notation ................... Condition Codes ....................Instruction Descriptions ................... S3P80C5/C80C5/C80C8 MICROCONTROLLER...
Page 8 Port 0 Interrupt Pending Register (P0PND)..................9-5 Port 1 ..............................9-7 Port 2 ..............................9-9 Chapter 10 Basic Timer and Timer 0 Module Overview.............................10-1 Basic Timer Control Register (BTCON) ....................10-1 Basic Timer Function Description ......................10-3 Timer 0 Control Register (T0CON) ......................10-3 Timer 0 Function Description.......................10-5 S3P80C5/C80C5/C80C8 MICROCONTROLLER...
Page 9 Timer 1 Match Interrupt ........................11-2 Timer 1 Control Register (T1CON) ....................11-4 Chapter 12 Counter A Overview ..............................12-1 Counter A Control Register (CACON)....................12-3 Counter A Pulse Width Calculations ....................12-4 Chapter 13 Electrical Data Overview ..............................13-1 Chapter 14 Mechanical Data Overview ..............................14-1 S3P80C5/C80C5/C80C8 viii MICROCONTROLLER...
Page 10 Indexed Addressing to Program or Data Memory with Short Offset ......3-8 Indexed Addressing to Program or Data Memory ...........3-9 3-10 Direct Addressing for Load Instructions ..............3-10 3-11 Direct Addressing for Call and Jump Instructions............3-11 3-12 Indirect Addressing....................3-12 3-13 Relative Addressing ....................3-13 3-14 Immediate Addressing....................3-14 Register Description Format ...................4-4 S3P80C5/C80C5/C80C8 MICROCONTROLLER...
Page 11 Reset Block Diagram....................8-1 Power-on Reset Circuit...................8-2 Timing Diagram for Power-on Reset Circuit............8-3 S3P80C5/C80C5/C80C8 I/O Port 0 Data Register Format........9-2 S3P80C5/C80C5/C80C8 I/O Port 1 Data Register Format........9-3 Port 0 High-Byte Control Register (P0CONH) ............9-4 Port 0 Low-Byte Control Register (P0CONL) ............9-5 Port 0 External Interrupt Control Register (P0INT) ..........9-6...
Page 12 Counter A Registers ....................12-4 12-4 Counter A Output Flip-Flop Waveforms in Repeat Mode........12-5 13-1 Input Timing for External Interrupts (Port 0)............13-5 13-2 Operating Voltage Range ..................13-6 14-1 24-Pin SOP Package Mechanical Data ..............14-1 14-2 24-Pin SDIP Package Mechanical Data..............14-2 S3P80C5/C80C5/C80C8 MICROCONTROLLER...
Page 14 Instruction Set Symbols..................6-8 Instruction Notation Conventions ................6-9 Opcode Quick Reference ..................6-10 Condition Codes.....................6-12 Set 1 Register Values After Reset ................8-4 Summary of Each Mode..................8-10 S3P80C5/C80C5/C80C8 Port Configuration Overview ...........9-1 Port Data Register Summary..................9-2 13-1 Absolute Maximum Ratings..................13-2 13-2 D.C. Electrical Characteristics ................13-2 13-3 Characteristics of Low Voltage Detect circuit ............13-4...
Page 16 To Divide STOP Mode Releasing and POR..................8-8 Chapter 10: Basic Timer and Timer 0 Configuring the Basic Timer ........................10-8 Programming Timer 0..........................10-9 Chapter 12: Counter A To Generate 38 kHz, 1/3duty Signal Through P2.1 ................12-6 To Generate a One Pulse Signal Through P2.1 ...................12-7 S3P80C5/C80C5/C80C8 MICROCONTROLLER...
Page 18 Port 2 Control Register ...................4-22 Register Page Pointer ....................4-23 Register Pointer 0....................4-24 Register Pointer 1....................4-24 Stack Pointer (Low Byte) ..................4-25 STOPCON Stop Control Register .....................4-25 System Mode Register ...................4-26 T0CON Timer 0 Control Register ..................4-27 T1CON Timer 1 Control Register ..................4-28 S3P80C5/C80C5/C80C8 MICROCONTROLLER xvii...
Page 20 Divide (Unsigned)....................6-38 DJNZ Decrement and Jump if Non-Zero ................6-39 Enable Interrupts ....................6-40 ENTER Enter ........................6-41 EXIT Exit ........................6-42 IDLE Idle Operation ......................6-43 Increment.......................6-44 INCW Increment Word .....................6-45 IRET Interrupt Return ......................6-46 Jump........................6-47 Jump Relative ......................6-48 Load........................6-49 Load Bit........................6-51 S3P80C5/C80C5/C80C8 MICROCONTROLLER...
Page 21 Subtract with Carry ....................6-77 Set Carry Flag ......................6-78 Shift Right Arithmetic....................6-79 SRP/SRP0/SRP1 Set Register Pointer ....................6-80 STOP Stop Operation .......................6-81 Subtract........................6-82 SWAP Swap Nibbles ......................6-83 Test Complement under Mask................6-84 Test under Mask.....................6-85 Wait for Interrupt ....................6-86 Logical Exclusive OR .....................6-87 S3P80C5/C80C5/C80C8 MICROCONTROLLER...
Page 22: Chapter 1 Product Overview
PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources —...
Page 23: Features
PRODUCT OVERVIEW S3P80C5/C80C5/C80C8 FEATURES Timers and Timer/Counters • One programmable 8-bit basic timer (BT) for • SAM87RC CPU core oscillation stabilization control or watchdog timer function Memory • • One 8-bit timer/counter (Timer 0) with two Program memory (ROM) operating modes; Interval mode and PWM mode.
Page 24: Block Diagram
S3P80C5/C80C5/C80C8 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7/INT0-INT4 P1.0-P1.7 Port 0(INTR) Port 1 TEST Internal Bus Main P2.0/T0PWM Port I/O and Interrupt Port 2 P2.1/REM Control 8-bit P2.2 Basic Timer SAM87RI CPU 8-bit Timer/ Counter Carrier Generator (Counter A) 256-Byte 15-Kbyte ROM...
Page 25: Pin Assignments
PRODUCT OVERVIEW S3P80C5/C80C5/C80C8 PIN ASSIGNMENTS P2.2 P2.1/REM/SCLK P2.0/T0PWN/T0CK/SDAT TEST P1.7 P0.0/INT0/INTR S3C80C5/C80C8 P1.6 P0.1/INT1/INTR RESET RESET/P0.2/INT2/INTR P1.5 24-SOP/SDIP P1.4 P0.3/INT3/INTR (TOP VIEW) P1.3 P0.4/INT4/INTR P1.2 P0.5/INT4/INTR P1.1 P0.6/INT4/INTR P1.0 P0.7/INT4/INTR Figure 1-2. Pin Assignment Diagram (24-Pin SOP/SDIP Package)
Page 26: Pin Descriptions
S3P80C5/C80C5/C80C8 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. Pin Descriptions Circuit 24-Pin Shared Names Type Description Type Number Functions P0.0–P0.7 I/O port with bit-programmable pins. 5–12 INT0 – INT4/INTR Configurable to input or push-pull output mode. Pull-up resistors are assignable by software.
Page 27: Pin Circuits
Figure 1-3. Pin Circuit Type 1 (Port 0) NOTE Interrupt with reset (INTR) is assigned to port 0 of S3P80C5/C80C5/C80C8. It is designed to release stop status with reset. When the falling/rising edge is detected at any pin of Port 0 during stop status, non vectored interrupt INTR signal occurs, after then system reset occurs automatically.
Page 28 S3P80C5/C80C5/C80C8 PRODUCT OVERVIEW Pull-up Resistor Pull-up Enable Data Input/Output Open-drain Output Disable Noise Normal filter Input Figure 1-4. Pin Circuit Type 2 (Port 1) Pull-up Resistor (Typical 21KΩ ) Pull-up Enable P2CON.0 Port 2.0 Data Data T0_PWN P2.0/T0PWN Open-drain Output Disable P2.0 Input...
Page 29 PRODUCT OVERVIEW S3P80C5/C80C5/C80C8 Pull-up Resistor (Typical 21KΩ) Pull-up Enable P2CON.1 Port 2.1 Data Data CAOF(CACON.0) Carrier On/Off (P2.5) P2.1/REM/T0CK Open-Drain Output Disable P2.1 Input T0CK Noise filter Figure 1-6. Pin Circuit Type 4 (P2.1) Pull-up Resistor (Typical 21KΩ) Pull-up Enable...
Page 30: Chapter 2 Address Spaces
S3P80C5/C80C5/C80C8 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3P80C5/C80C5/C80C8 microcontroller has two types of address space: — Internal program memory (ROM) — Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file.
Page 31: Program Memory (Rom)
ADDRESS SPACES S3P80C5/C80C5/C80C8 PROGRAM MEMORY (ROM) Program memory stores program code or table data. The S3C80C5 has 15, 872 bytes of internal programmable program memory, and the program memory address range is therefore 0000H-3E00H of ROM. The S3C80C8 has 8-Kbyte (0000H-1FFFH) of internal programmable program memory (see Figure 2-1).
Page 32: Register Architecture
ADDRESS SPACES REGISTER ARCHITECTURE The S3P80C5/C80C5/C80C8 register file has 312 registers. The upper 64 bytes register files are addressed as system control register and working register. The lower 192-byte area of the physical register file(00H–BFH) contains freely-addressable, general-purpose registers called prime registers. It can be also used for stack operation.
Page 33 ADDRESS SPACES S3P80C5/C80C5/C80C8 Set 1 Set 2 System and Peripheral Control Registers (Register Addressing General-Purpose Mode) Data Register (Indirect Register or 64-Bytes System Registers Indexed addressing (Register Addressing modes or Mode) stack operations) Working Registers (Working Register Addressing Mode) 256-Bytes...
Page 34: Register Page Pointer (Pp)
8-bit data bus) into as many as 15 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3P80C5/C80C5/C80C8 microcontroller, a paged register file expansion is not implemented and the register page pointer settings therefore always point to "page 0."...
Page 35: Register Set 1
32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to address one bank or the other. In the S3P80C5/C80C5/C80C8 microcontroller, bank 1 is not implemented. A hardware reset operation therefore always selects bank 0 addressing, and the SB0 and SB1 instructions are not necessary.
Page 36: Prime Register Space
S3P80C5/C80C5/C80C8 ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) is called the prime register space or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.) All...
Page 37: Working Registers
ADDRESS SPACES S3P80C5/C80C5/C80C8 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of 32 8-byte register groups or "slices."...
Page 38: Using The Register Pointers
S3P80C5/C80C5/C80C8 ADDRESS SPACES USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
Page 39 ADDRESS SPACES S3P80C5/C80C5/C80C8 F7H (R7) 8-Byte Slice F0H (R0) 16-Byte Register File Contiguous Contains 32 1 1 1 1 0 X X X working 8-Byte Slices Register block 7H (R15) 0 0 0 0 0 X X X 8-Byte Slice 0H (R0) Figure 2-7.
Page 40: Register Addressing
S3P80C5/C80C5/C80C8 ADDRESS SPACES REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access all locations in the register file except for set 2.
Page 41 ADDRESS SPACES S3P80C5/C80C5/C80C8 Special-Purpose Registers General-Purpose Register Set 1 Control Registers Set 2 System Registers Register Pointers Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file Prime (other than set 2). After a reset, RP0 points to...
Page 42: Common Working Register Area (C0H-Cfh)
S3P80C5/C80C5/C80C8 ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area.
Page 43: 4-Bit Working Register Addressing
ADDRESS SPACES S3P80C5/C80C5/C80C8 PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Example 1: 0C2H,40H ; Invalid addressing mode!
Page 44 S3P80C5/C80C5/C80C8 ADDRESS SPACES Selects RP0 or RP1 Address OPCODE 4-bit Address Register Pointer Provides Three Provides Five Low-order Bits High-order Bits Together They Create an 8-bit Register Address Figure 2-11. 4-Bit Working Register Addressing 0 1 1 1 0 0 0 0...
Page 45: 8-Bit Working Register Addressing
ADDRESS SPACES S3P80C5/C80C5/C80C8 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100B.
Page 46 S3P80C5/C80C5/C80C8 ADDRESS SPACES 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 Selects RP1 8-bit Address Form Instruction 1 1 0 0 0 1 1 'LD R11, R2' Specifies Working Register Addressing Register Address (0ABH)
Page 47: System And User Stacks
Register location D9H contain the 8-bit stack pointer (SPL) that is used for system stack operations. After a reset, the SPL value is undetermined. Because only internal memory 256-byte is implemented in S3P80C5/C80C5/C80C8, the SPL must be initialized to an 8-bit value in the range 00H–FFH. 2-18...
Page 48 S3P80C5/C80C5/C80C8 ADDRESS SPACES PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SPL ← FFH SPL,#0FFH ; (Normally, the SPL is set to 0FFH by the initialization ;...
Page 49 ADDRESS SPACES S3P80C5/C80C5/C80C8 NOTES 2-20...
Page 50: Chapter 3 Addressing Modes
S3P80C5/C80C5/C80C8 ADDRESSING MODES ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memory for execution. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.
Page 51: Register Addressing Mode (R)
ADDRESSING MODES S3P80C5/C80C5/C80C8 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing because it uses a register pointer to specify an 8- byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Page 52: Indirect Register Addressing Mode (Ir)
S3P80C5/C80C5/C80C8 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).
Page 53 ADDRESSING MODES S3P80C5/C80C5/C80C8 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Register Pair Instruction Points to References OPCODE Register Pair Program 16-Bit Memory Address Points to Program Program Memory Memory Sample Instructions: Value used in OPERAND Instruction CALL...
Page 54 S3P80C5/C80C5/C80C8 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP Points to Start of Program Memory Woking Register 4-bit Block 3 LSBs Working ADDRESS Register Point to the OPCODE...
Page 55 ADDRESSING MODES S3P80C5/C80C5/C80C8 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP Points to Start of Working Program Memory Register 4-bit Working Block Register Address Register Next 2-bit Point Pair OPCODE...
Page 56: Indexed Addressing Mode (X)
S3P80C5/C80C5/C80C8 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory (if implemented).
Page 57 ADDRESSING MODES S3P80C5/C80C5/C80C8 INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP Points to Start of Working Program Memory Register Block OFFSET Next 2 Bits 4 Bit Working dst/src Register Register Address...
Page 58 S3P80C5/C80C5/C80C8 ADDRESSING MODES INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP Points to Start of Program Memory Working Register OFFSET Block OFFSET Next 2 Bits 4 Bit Working dst/src Register Register Address...
Page 59: Direct Address Mode (Da)
ADDRESSING MODES S3P80C5/C80C5/C80C8 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
Page 60 S3P80C5/C80C5/C80C8 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY ; Where DISPLAY is a 16 bit immediate address Figure 3-11.
Page 61: Indirect Address Mode (Ia)
ADDRESSING MODES S3P80C5/C80C5/C80C8 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Page 62: Relative Address Mode (Ra)
S3P80C5/C80C5/C80C8 ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.
Page 63: Immediate Mode (Im)
ADDRESSING MODES S3P80C5/C80C5/C80C8 IMMEDIATE MODE (IM) In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.
Page 64: Overview
CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3P80C5/C80C5/C80C8 control registers are presented in an easy-to- read format. You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.
Page 65 CONTROL REGISTERS S3P80C5/C80C5/C80C8 Table 4-1. Mapped Registers (Set 1) Register Name Mnemonic Decimal (note) Timer 0 counter T0CNT Timer 0 data register T0DATA Timer 0 control register T0CON Basic timer control register BTCON Clock control register CLKCON System flags register...
Page 66 S3P80C5/C80C5/C80C8 CONTROL REGISTERS Table 4-1. Mapped Registers (Continued) Register Name Mnemonic Decimal Timer 1 data register (low byte) T1DATAL Timer 1 control register T1CON STOP Control register STOPCON Locations FCH is not mapped. (note) Basic timer counter BTCNT External memory timing register Interrupt priority register NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
Page 67 CONTROL REGISTERS S3P80C5/C80C5/C80C8 Bit number(s) that is/are appended to Name of individual the register name for bit addressing bit or related bits Register location in the internal Register address Register ID Register name (hexadecimal) register file FLAGS - System Flags Register...
Page 68 .3–.2 Basic Timer Input Clock Selection Bits /4096 /1024 /128 Invalid setting; not used for S3P80C5/C80C5/C80C8. Basic Timer Counter Clear Bit No effect Clear the basic timer counter value Clock Frequency Divider Clear Bit for Basic Timer and Timer 0...
Page 69 CONTROL REGISTERS S3P80C5/C80C5/C80C8 CACON — Counter A Control Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 Counter A Input Clock Selection Bits .5–.4 Counter A Interrupt Timing Selection Bits Elapsed time for Low data value...
Page 70 CLKCON.3 and CLKCON.4. These selection bits are required only for systems that have a main clock and a subsystem clock. The S3P80C5/C80C5/C80C8 uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.
Page 71: Emt External Memory Timing Register
Select external data memory area Not used for S3P80C5/C80C5/C80C8. NOTE: The EMT register is not used for S3P80C5/C80C5/C80C8, because an external peripheral interface is not implemented in the S3P80C5/C80C5/C80C8. The program initialization routine should clear the EMT register to '00H' following a reset. Modification of EMT...
Page 72 S3P80C5/C80C5/C80C8 CONTROL REGISTERS FLAGS — System Flags Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only Carry Flag (C) Operation does not generate a carry or borrow condition Operation generates a carry-out or borrow into high-order bit 7...
Page 73: Imr Interrupt Mask Register
Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow Disable (mask) Enable (un-mask) NOTES: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU. Interrupt levels IRQ2, IRQ3 and IRQ5 are not used in the S3P80C5/C80C5/C80C8 interrupt structure. 4-10...
Page 74: Iph Instruction Pointer (High Byte)
S3P80C5/C80C5/C80C8 CONTROL REGISTERS — Instruction Pointer (High Byte) Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8).
Page 75: Ipr Interrupt Priority Register
IRQ0 > IRQ1 IRQ1 > IRQ0 NOTE: The S3P80C5/C80C5/C80C8 interrupt structure uses only five levels: IRQ0, IRQ1, IRQ4, IRQ6–IRQ7. Because IRQ2, IRQ3, IRQ5 are not recognized, the interrupt subgroup B and group C settings (IPR.2,.3 and IPR.5) are not evaluated.
Page 76: Irq Interrupt Request Register
Level 1 (IRQ1) Request Pending Bit; Timer 1 Match or Overflow Not pending Pending Level 0 (IRQ0) Request Pending Bit; Timer 0 Match or Overflow Not pending Pending NOTE: Interrupt level IRQ2, IRQ3 and IRQ5 is not used in the S3P80C5/C80C5/C80C8 interrupt structure. 4-13...
Page 77 CONTROL REGISTERS S3P80C5/C80C5/C80C8 P0CONH — Port 0 Control Register (High Byte) Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P0.7/INT4 Mode Selection Bits C-MOS input mode; interrupt on falling edges C-MOS input mode; interrupt on rising and falling edges Push-pull output mode C-MOS input mode;...
Page 78 S3P80C5/C80C5/C80C8 CONTROL REGISTERS P0CONL — Port 0 Control Register (Low Byte) Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P0.3/INT3 Mode Selection Bits C-MOS input mode; interrupt on falling edges C-MOS input mode; interrupt on rising and falling edges Push-pull output mode C-MOS input mode;...
Page 79 CONTROL REGISTERS S3P80C5/C80C5/C80C8 P0INT — Port 0 External Interrupt Enable Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only P0.7 External Interrupt (INT4) Enable Bit Disable interrupt Enable interrupt P0.6 External Interrupt (INT4) Enable Bit...
Page 80 S3P80C5/C80C5/C80C8 CONTROL REGISTERS P0PND — Port 0 External Interrupt Pending Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only (note) P0.7 External Interrupt (INT4) Pending Flag No P0.7 external interrupt pending (when read) P0.7 external interrupt is pending (when read) P0.6 External Interrupt (INT4) Pending Flag...
Page 81 CONTROL REGISTERS S3P80C5/C80C5/C80C8 P0PUR — Port 0 Pull-up Resistor Enable Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only P0.7 Pull-up Resistor Enable Bit Enable pull-up resistor Disable pull-up resistor P0.6 Pull-up Resistor Enable Bit...
Page 82 S3P80C5/C80C5/C80C8 CONTROL REGISTERS P1CONH — Port 1 Control Register (High Byte) Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P1.7 Mode Selection Bits C-MOS input mode Open-drain output mode Push-pull output mode Invalid setting .5–.4...
Page 83 CONTROL REGISTERS S3P80C5/C80C5/C80C8 P1CONL — Port 1 Control Register (Low Byte) Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P1.3 Mode Selection Bits C-MOS input mode Open-drain output mode Push-pull output mode Invalid setting .5–.4...
Page 84 S3P80C5/C80C5/C80C8 CONTROL REGISTERS P1PUR — Port 0 Pull-up Resistor Enable Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only P1.7 Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P1.6 Pull-up Resistor Enable Bit...
Page 85 CONTROL REGISTERS S3P80C5/C80C5/C80C8 P2CON — Port 2 Control Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P2.2 Mode Selection Bits C-MOS input mode Open-drain output mode Push-pull output mode C-MOS input with pull up mode .5–.4...
Page 86: Pp Register
(note) Source: page 0 NOTE: In the S3P80C5/C80C5/C80C8 microcontroller, a paged expansion of the internal register file is not implemented. For this reason, only page 0 settings are valid. Register page pointer values for the source and destination register page are automatically set to '0000B' following a hardware reset. These values should not be changed during normal operation.
Page 87: Rp0 Register Pointer 0
8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H–C7H. .2–.0 Not used for S3P80C5/C80C5/C80C8. — Register Pointer 1 Set 1 Bit Identifier...
Page 88: Spl Stack Pointer (Low Byte)
S3P80C5/C80C5/C80C8 CONTROL REGISTERS — Stack Pointer (Low Byte) Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.0 Stack Pointer Address (Low Byte) The SP value is undefined following a reset. STOPCON — Stop Control Register...
Page 89: Sym System Mode Register
Enable global interrupt processing NOTES: Because an external interface is not implemented for the S3P80C5/C80C5/C80C8, SYM.7 must always be "0". You can select only one interrupt level at a time for fast interrupt processing. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.
Page 90 S3P80C5/C80C5/C80C8 CONTROL REGISTERS T0CON — Timer 0 Control Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 Timer 0 Input Clock Selection Bits /4096 /256 External clock input (at the T0CK pin, P2.1) .5–.4...
Page 91 CONTROL REGISTERS S3P80C5/C80C5/C80C8 T1CON — Timer 1 Control Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 Timer 1 Input Clock Selection Bits Internal clock (counter a flip-flop, T-FF) .5–.4 Timer 1 Operating Mode Selection Bits...
Page 92: Interrupt Structure
The maximum number of vectors that can be supported for a given level is 128. (The actual number of vectors used for S3C8-series devices is always much smaller.) If an interrupt level has more than one vector address, the vector priorities are set in hardware. The S3P80C5/C80C5/C80C8 uses ten vectors. One vector address is shared by four interrupt sources.
Page 93 In the S3P80C5/C80C5/C80C8 microcontroller, all three interrupt types are implemented. Levels Vectors Sources Type 1: IRQn Type 2: IRQn Type 3: IRQn NOTES: The number of S and V value is expandable. In the S3P80C5/C80C5/C80C8 implementation, interrupt types 1, 2, and 3 is used. Figure 5-1. S3C8-Series Interrupt Types...
Page 94 — Vectored Interrupt — Non vectored interrupt (Reset interrupt): INTR The S3P80C5/C80C5/C80C8 microcontroller supports thirteen interrupt sources. Nine of the interrupt sources have a corresponding interrupt vector address; the remaining four interrupt sources share the same vector address. Five interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.
Page 95 For interrupt levels with two or more vectors, the lowest vector address usually the highest priority. For example, FAH has the higher priority (0) than FCH (1) within level IRQ0. These priorities are fixed in hardware. Figure 5-2. S3P80C5/C80C5/C80C8 Interrupt Structure...
Page 96: Interrupt Vector Addresses
INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3P80C5/C80C5/C80C8 interrupt structure are stored in the vector address area of the internal program memory ROM, 00H–FFH. You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses.
Page 97 INTERRUPT STRUCTURE S3P80C5/C80C5/C80C8 Table 5-1. S3P80C5/C80C5/C80C8 Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Interrupt Priority in Value Value Level Level RESET √ 100H Basic timer overflow – √ Timer 0 (match) IRQ0 √ Timer 0 overflow √ Timer 1 (match) IRQ1 √...
Page 98: Enable/Disable Interrupt Instructions (Ei, Di)
Interrupt priority register Controls the relative processing priorities of the interrupt levels. The five levels of the S3P80C5/C80C5/C80C8 are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ4, and group C is IRQ6, and IRQ7.
Page 99 INTERRUPT STRUCTURE S3P80C5/C80C5/C80C8 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are, therefore: — Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 ) —...
Page 100 S3P80C5/C80C5/C80C8 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers...
Page 101: System Mode Register (Sym)
INTERRUPT STRUCTURE S3P80C5/C80C5/C80C8 SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5). A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2, is undetermined.
Page 102: Interrupt Mask Register (Imr)
S3P80C5/C80C5/C80C8 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
Page 103: Interrupt Priority Register (Ipr)
3, and 4. IPR.3 defines the possible subgroup B relationships. IPR.2 controls interrupt group B. In the S3P80C5/C80C5/C80C8 implementation, interrupt levels 2 and 3 are not used. Therefore, IPR.2 and IPR.3 settings are not evaluated, as IRQ4 is the only remaining level in the group.
Page 104 S3P80C5/C80C5/C80C8 INTERRUPT STRUCTURE Interrupt Priority Register (IPR) FFH, Set 1, Bank 0, R/W Group priority: Group A 0 = IRQ0 > IRQ1 D7 D4 D1 1 = IRQ1 > IRQ0 (note) Group B = Undefined 0 = IRQ4 = B > C > A 1 = IRQ4 = A >...
Page 105: Interrupt Request Register (Irq)
INTERRUPT STRUCTURE S3P80C5/C80C5/C80C8 INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on.
Page 106: Interrupt Pending Function Types
"0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software. In the S3P80C5/C80C5/C80C8 interrupt structure, the timer 0 and timer 1 overflow interrupts (IRQ0 and IRQ1), and the counter A interrupt (IRQ4) belong to this category of interrupts whose pending condition is cleared automatically by hardware.
Page 107: Interrupt Source Polling Sequence
INTERRUPT STRUCTURE S3P80C5/C80C5/C80C8 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source.
Page 108: Generating Interrupt Vector Addresses
S3P80C5/C80C5/C80C8 INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack.
Page 109 — When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' ("FLAGS prime"). NOTE For the S3P80C5/C80C5/C80C8 microcontroller, the service routine for any one of the five interrupt levels: IRQ0, IRQ1, IRQ4 or IRQ6–IRQ7, can be selected for fast interrupt processing. Procedure for Initiating Fast Interrupts To initiate fast interrupt processing, follow these steps: 1.
Page 110: Overview
S3P80C5/C80C5/C80C8 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: —...
Page 111 INSTRUCTION SET S3P80C5/C80C5/C80C8 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst, src Load dst, src Load bit dst, src Load external data memory dst, src Load program memory LDED dst, src Load external data memory and decrement...
Page 112 S3P80C5/C80C5/C80C8 INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions dst,src Add with carry dst,src dst,src Compare Decimal adjust Decrement DECW Decrement word dst,src Divide Increment INCW Increment word MULT dst,src Multiply dst,src Subtract with carry...
Page 113 INSTRUCTION SET S3P80C5/C80C5/C80C8 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL Call procedure CPIJE dst,src Compare, increment and jump on equal...
Page 114 S3P80C5/C80C5/C80C8 INSTRUCTION SET Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic SWAP Swap nibbles CPU Control Instructions Complement carry flag...
Page 115 INSTRUCTION SET S3P80C5/C80C5/C80C8 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic.
Page 116 S3P80C5/C80C5/C80C8 INSTRUCTION SET FLAG DESCRIPTIONS Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.
Page 117 INSTRUCTION SET S3P80C5/C80C5/C80C8 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation –...
Page 118 S3P80C5/C80C5/C80C8 INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Bit (b) of working register Rn.b (n = 0–15, b = 0–7) Bit 0 (LSB) of working register Rn (n = 0–15)
Page 119 INSTRUCTION SET S3P80C5/C80C5/C80C8 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1.b, R2 BXOR r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb SRP/0/1 BTJR IRR1 r1,r2 r1,Ir2 R2,R1...
Page 120 S3P80C5/C80C5/C80C8 INSTRUCTION SET Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – DJNZ NEXT r1,R2 r2,R1 r1,RA cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ ↓ ENTER EXIT IDLE ↓ ↓ ↓ ↓ ↓ ↓ ↓...
Page 121 INSTRUCTION SET S3P80C5/C80C5/C80C8 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"...
Page 122 S3P80C5/C80C5/C80C8 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...
Page 123 INSTRUCTION SET S3P80C5/C80C5/C80C8 — Add with carry dst,src dst ← dst + src + c Operation: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed.
Page 124: Add Add
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
Page 125: And Logical And
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...
Page 126: Band Bit And
S3P80C5/C80C5/C80C8 INSTRUCTION SET BAND — Bit AND BAND dst,src.b BAND dst.b,src dst(0) ← dst(0) AND src(b) Operation: dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source).
Page 127: Bcp Bit Compare
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Bit Compare dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.
Page 128: Bitc Bit Complement
S3P80C5/C80C5/C80C8 INSTRUCTION SET BITC — Bit Complement BITC dst.b dst(b) ← NOT dst(b) Operation: This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
Page 129: Bitr Bit Reset
INSTRUCTION SET S3P80C5/C80C5/C80C8 BITR — Bit Reset BITR dst.b dst(b) ← 0 Operation: The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode...
Page 130: Bits Bit Set
S3P80C5/C80C5/C80C8 INSTRUCTION SET BITS — Bit Set BITS dst.b dst(b) ← 1 Operation: The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode...
Page 131: Bor Bit Or
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Bit OR dst,src.b dst.b,src dst(0) ← dst(0) OR src(b) Operation: dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination.
Page 132: Btjrf Bit Test, Jump Relative On False
S3P80C5/C80C5/C80C8 INSTRUCTION SET BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b If src(b) is a "0", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...
Page 133: Btjrt Bit Test, Jump Relative On True
INSTRUCTION SET S3P80C5/C80C5/C80C8 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b If src(b) is a "1", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...
Page 134: Bxor Bit Xor
S3P80C5/C80C5/C80C8 INSTRUCTION SET BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src dst(0) ← dst(0) XOR src(b) Operation: dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected.
Page 135: Call Call Procedure
INSTRUCTION SET S3P80C5/C80C5/C80C8 CALL — Call Procedure CALL ← Operation: SP – 1 ← ← SP –1 ← ← The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
Page 136: Ccf Complement Carry Flag
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
Page 137: Clr Clear
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Clear dst ← "0" Operation: The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: →...
Page 138: Com Complement
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
Page 139: Cp Compare
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Compare dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Page 140: Cpije Compare, Increment, And Jump On Equal
S3P80C5/C80C5/C80C8 INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA If dst – src = "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter.
Page 141: Cpijne Compare, Increment, And Jump On Non-Equal
INSTRUCTION SET S3P80C5/C80C5/C80C8 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA If dst – src "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement...
Page 142 S3P80C5/C80C5/C80C8 INSTRUCTION SET — Decimal Adjust dst ← DA dst Operation: The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not...
Page 143: Decimal Adjust
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Decimal Adjust (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH R1,R0 R1 ←...
Page 144: Dec Decrement
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise.
Page 145: Decw Decrement Word
INSTRUCTION SET S3P80C5/C80C5/C80C8 DECW — Decrement Word DECW dst ← dst – 1 Operation: The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one.
Page 146: Di Disable Interrupts
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Disable Interrupts SYM (0) ← 0 Operation: Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
Page 147: Div Divide (Unsigned)
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Divide (Unsigned) dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination.
Page 148: Djnz Decrement And Jump If Non-Zero
S3P80C5/C80C5/C80C8 INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst r ← r – 1 Operation: If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.
Page 149: Ei Enable Interrupts
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Enable Interrupts SYM (0) ← 1 Operation: An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
Page 150 S3P80C5/C80C5/C80C8 INSTRUCTION SET ENTER — Enter ENTER ← Operation: SP – 2 ← ← ← ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer.
Page 151: Exit Exit
INSTRUCTION SET S3P80C5/C80C5/C80C8 EXIT — Exit EXIT ← Operation: ← SP + 2 ← ← IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.
Page 152: Idle Idle Operation
S3P80C5/C80C5/C80C8 INSTRUCTION SET IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected.
Page 153: Inc Increment
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.
Page 154: Incw Increment Word
S3P80C5/C80C5/C80C8 INSTRUCTION SET INCW — Increment Word INCW dst ← dst + 1 Operation: The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.
Page 155: Iret Interrupt Return
INSTRUCTION SET S3P80C5/C80C5/C80C8 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) FLAGS ← @SP PC ↔ IP Operation: SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine.
Page 156: Jp Jump
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.
Page 157: Jr Jump Relative
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...
Page 158: Ld Load
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc...
Page 159 INSTRUCTION SET S3P80C5/C80C5/C80C8 — Load (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0,#10H R0 = 10H →...
Page 160 S3P80C5/C80C5/C80C8 INSTRUCTION SET — Load Bit dst,src.b dst.b,src dst(0) ← src(b) Operation: dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected.
Page 161: Ldc/Lde Load Memory
INSTRUCTION SET S3P80C5/C80C5/C80C8 LDC/LDE — Load Memory LDC/LDE dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory.
Page 162 S3P80C5/C80C5/C80C8 INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: ;...
Page 163: Ldcd/Lded Load Memory And Decrement
INSTRUCTION SET S3P80C5/C80C5/C80C8 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
Page 164: Ldci/Ldei Load Memory And Increment
S3P80C5/C80C5/C80C8 INSTRUCTION SET LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
Page 165 INSTRUCTION SET S3P80C5/C80C5/C80C8 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src rr ← rr – 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented.
Page 166 S3P80C5/C80C5/C80C8 INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src rr ← rr + 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented.
Page 167: Ldw Load Word
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Load Word dst,src dst ← src Operation: The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode...
Page 168: Mult Multiply (Unsigned)
S3P80C5/C80C5/C80C8 INSTRUCTION SET MULT — Multiply (Unsigned) MULT dst,src dst ← dst × src Operation: The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.
Page 169 INSTRUCTION SET S3P80C5/C80C5/C80C8 NEXT — Next NEXT PC ← @ IP Operation: IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.
Page 170: Nop No Operation
S3P80C5/C80C5/C80C8 INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected.
Page 171: Or Logical Or
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...
Page 172: Pop Pop From Stack
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.
Page 173: Popud Pop User Stack (Decrementing)
INSTRUCTION SET S3P80C5/C80C5/C80C8 POPUD — Pop User Stack (Decrementing) POPUD dst,src dst ← src Operation: IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.
Page 174: Popui Pop User Stack (Incrementing)
S3P80C5/C80C5/C80C8 INSTRUCTION SET POPUI — Pop User Stack (Incrementing) POPUI dst,src dst ← src Operation: IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.
Page 175 INSTRUCTION SET S3P80C5/C80C5/C80C8 PUSH — Push To Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.
Page 176: Pushud Push User Stack (Decrementing)
S3P80C5/C80C5/C80C8 INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src IR ← IR – 1 Operation: dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.
Page 177: Pushui Push User Stack (Incrementing)
INSTRUCTION SET S3P80C5/C80C5/C80C8 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src IR ← IR + 1 Operation: dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.
Page 178: Rcf Reset Carry Flag
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
Page 179: Ret Return
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
Page 180: Rl Rotate Left
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
Page 181: Rlc Rotate Left Through Carry
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Rotate Left Through Carry dst (0) ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...
Page 182: Rr Rotate Right
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
Page 183: Rrc Rotate Right Through Carry
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Rotate Right Through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...
Page 184: Sb0 Select Bank 0
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Select Bank 0 BANK ← 0 Operation: The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file.
Page 185: Sb1 Select Bank 1
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Select Bank 1 BANK ← 1 Operation: The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some KS88-series microcontrollers.)
Page 186: Sbc Subtract With Carry
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Subtract With Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
Page 187: Scf Set Carry Flag
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex)
Page 188: Sra Shift Right Arithmetic
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.
Page 189: Srp/Srp0/Srp1
INSTRUCTION SET S3P80C5/C80C5/C80C8 SRP/SRP0/SRP1 — Set Register Pointer SRP0 SRP1 ← Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) src (3–7) ← If src (1) = 0 and src (0) = 1 then: RP1 (3–7) src (3–7)
Page 190: Stop Stop Operation
S3P80C5/C80C5/C80C8 INSTRUCTION SET STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.
Page 191: Sub Subtract
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
Page 192: Swap Swap Nibbles
S3P80C5/C80C5/C80C8 INSTRUCTION SET SWAP — Swap Nibbles SWAP dst (0 – 3) ↔ dst (4 – 7) Operation: The contents of the lower four bits and upper four bits of the destination operand are swapped. Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise.
Page 193: Tcm Test Complement Under Mask
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Test Complement Under Mask dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
Page 194: Tm Test Under Mask
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.
Page 195: Wfi Wait For Interrupt
INSTRUCTION SET S3P80C5/C80C5/C80C8 — Wait For Interrupt Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt .
Page 196: Xor Logical Exclusive Or
S3P80C5/C80C5/C80C8 INSTRUCTION SET — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...
Page 197 INSTRUCTION SET S3P80C5/C80C5/C80C8 NOTES 6-88...
Page 198 CLOCK CIRCUITS OVERVIEW The clock frequency generated for the S3P80C5/C80C5/C80C8 by an external crystal, or supplied by an external clock source, can range from 1MHz to 4 MHz. The maximum CPU clock frequency, as determined by CLKCON register settings, is 4 MHz. The X...
Page 199 CLOCK CIRCUITS S3P80C5/C80C5/C80C8 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by Power On Reset operation or by a non-vectored interrupt - interrupt with reset (INTR).
Page 200 CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release. (This is called the "IRQ wake-up" function.) The IRQ wake-up enable bit is CLKCON.7. In S3P80C5/C80C5/C80C8, this bit is not valid any more. Actually bit 7, 6, 5, 2, 1, and 0 are no meaning in S3P80C5/C80C5/C80C8.
Page 201 CLOCK CIRCUITS S3P80C5/C80C5/C80C8 NOTES...
Page 202 Figure 8-1. Reset Block Diagram LVD RESET The Low Voltage detect circuit is built on the S3P80C5/C80C5/C80C8 product for system reset not in stop mode. When the operating status is not stop mode it detects a slope of V by comparing the voltage at V with V (Low level Detect Voltage).
Page 203 System reset can return to the proper operation of chip. POWER-ON RESET(POR) The power-on reset circuit is built on the S3P80C5/C80C5/C80C8 product. During a power-on reset, the voltage at V goes to High level and the Schmitt trigger input of POR circuit is forced to Low level and then to High level.
Page 204 System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal CPU and peripheral modules. This procedure brings the S3P80C5/C80C5/C80C8 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance.
Page 205 RESET RESET and POWER-DOWN S3P80C5/C80C5/C80C8 HARDWARE RESET VALUES Tables 5-1 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: — A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
Page 206 Interrupt priority register NOTES: Although the SYM register is not used for the S3P80C5/C80C5/C80C8, SYM.5 should always be "0". If you accidentally write a 1 to this bit during normal operation, a system malfunction may occur. Except for T0CNT, IRQ, T1CNTH, T1CNTL, and BTCNT, which are read-only, all registers in set 1 are read/write addressable.
Page 207 RESET RESET and POWER-DOWN S3P80C5/C80C5/C80C8 POWER-DOWN MODES STOP MODE Stop mode is invoked by stop control register (STOPCON) setting and the instruction STOP. In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3 uA at 5.5 V.
Page 208 RESET RESET S3P80C5/C80C5/C80C8 and POWER-DOWN PROGRAMMING TIP — To Divide STOP Mode Releasing and POR. This example shows how to enter the stop mode and how to know it is stop mode releasing or power on RESET. 0100H ; Reset address...
Page 209 RESET RESET and POWER-DOWN S3P80C5/C80C5/C80C8 PROGRAMMING TIP — To Divide STOP Mode Releasing and POR. (Continued) CHK_W @R0,R0 R0,#0B0H UGE,CHK_W MAIN: P0,#0FFH EQ,ENT_STOP • • • T,MAIN ENT_STOP STOPCON,#0A5H ;Enter the STOP mode. STOP RESET • • •...
Page 210 RESET RESET S3P80C5/C80C5/C80C8 and POWER-DOWN IDLE MODE Idle mode is invoked by the instruction IDLE (OPCODE 6FH). In Idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU and from all but the following peripherals, which remain active: —...
Page 211 RESET RESET and POWER-DOWN S3P80C5/C80C5/C80C8 SUMMARY TABLE OF STOP MODE, AND IDLE MODE Table 8-2. Summary of Each Mode Item/Mode IDLE STOP < V < V Approach Condition is higher than V is higher than V STOPCON ≤ A5H IDLE (instruction).
Page 212 The S3P80C5/C80C5/C80C8 microcontroller has three bit-programmable I/O ports, P0–P2. Two ports, P0-P1, are 8-bit ports and P2 is a 3-bit port. This gives a total of 19 I/O pins in the S3P80C5/C80C5/C80C8"s 24-pin package. Each port is bit-programmable and can be flexibly configured to meet application design requirements.
Page 213 Because port 2 is a 3-bit I/O port, the port 2 data register only contains values for P2.0, P2.1 and P2.2. The P2 register also contains values for P2.0, P2.1 and P2.2. The P2 register also contains a special carrier on/off bit(P2.5). See the port 2 description for details. All other S3P80C5/C80C5/C80C8 I/O ports are 8-bit. PULL-UP RESISTOR ENABLE REGISTERS...
Page 214 0 = Disable pull-up resistor 1 = Enable pull-up resistor NOTE: Pull-up resistors can be assigned to the port 2 pins, P2.0, P2.1 and P2.2 by marking the appropriate the port 2 control register, P2CON. Figure 9-2. S3P80C5/C80C5/C80C8 I/O Port 1 Data Register Format...
Page 215 I/O PORTS S3P80C5/C80C5/C80C8 PORT 0 Port 0 is a general-purpose, 8-bit I/O port. It is bit-programmable. Port 0 pins are accessed directly by read/write operations to the port 0 data register, P0 (set 1, E0H). The P0 pin circuits support pull-up resistor assignment using P0PUR register settings and all pins have noise filters for external interrupt inputs.
Page 216 S3P80C5/C80C5/C80C8 I/O PORTS Port 0 Control Register, Low Byte (P0CONL) E9H, Set 1, R/W P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0CONL Pin Configureation Settings: Input mode; interrupt on falling edges Input mode; interrupt on rising and falling edges Push-pull output mode Input mode; interrupt on rising edges Figure 9-4.
Page 217 I/O PORTS S3P80C5/C80C5/C80C8 Port 0 Interrup Enable Register (P0INT) F1H, Set 1, R/W P0.6/INT4 P0.4/INT4 P0.2/INT2 P0.0/INT0 P0.7/INT4 P0.5/INT4 P0.3/INT3 P0.1/INT1 Port 0 Interrupt Enable Bits: Disable interrupt Enable interrupt Figure 9-5. Port 0 External Interrupt Control Register (P0INT) Port 0 Interrup Pending Register (P0PND) F2H, Set 1, R/W P0.6/INT4...
Page 218 S3P80C5/C80C5/C80C8 I/O PORTS PORT 1 Port 1 is a bit-programmable 8-bit I/O port. Port 1 pins are accessed directly by read/write operations to the port 1 data register, P1 (set 1, E1H). To configure port 1, the initialization routine writes the appropriate values to the two port 1 control registers: P1CONH (set 1, EAH) for the upper nibble pins, P1.7–P1.4, and P1CONL (set 1, EBH) for the lower nibble pins,...
Page 219 I/O PORTS S3P80C5/C80C5/C80C8 Port 1 Control Register, Low Byte (P1CONL) EBH, Set 1, R/W P1.0 P1.1 P1.2 P1.3 P1CONL Pin Configureation Settings: Input mode Open-drain output mode Push-pull output mode Invalid setting Figure 9-8. Port 1 Low-Byte Control Register (P1CONL)
Page 220 S3P80C5/C80C5/C80C8 I/O PORTS PORT 2 Port 2 is a bit-programmable 3-bit I/O port. Port 2 pins are accessed directly by read/write operations to the port 2 data register, P2 (set 1, E2H). You can configure port 2 pins individually to Input mode, open-drain output mode, or push-pull output mode.
Page 221 I/O PORTS S3P80C5/C80C5/C80C8 Port 2 Data Register (P2) E2H, R/W P2.0/T0_PWM Not used for S3C80C5 P2.1/REM/TOCK Carrier on/off for Remote Controller P2.2 Not used for S3C80C5 Figure 9-10. Port 2 Data Register (P2) 9-10...
Page 222 BASIC TIMER AND TIMER 0 BASIC TIMER and TIMER 0 MODULE OVERVIEW The S3P80C5/C80C5/C80C8 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The 8-bit timer/counter is called timer 0. Basic Timer (BT) You can use the basic timer (BT) in two different ways: —...
Page 223 BASIC TIMER and TIMER 0 S3P80C5/C80C5/C80C8 Basic Timer Control Register (BTCON) D3H, Set 1, R/W Watchdog function enable bits: Divider clear bit for basic 1010B = Disable watchdog timer timer and timer 0: Other value = Enable watchdog timer 0 = No effect...
Page 224 S3P80C5/C80C5/C80C8 BASIC TIMER AND TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by enabling the watchdog function. A reset clears BTCON to '00H', automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting),divided by 4096, as the BT clock.
Page 225 BASIC TIMER and TIMER 0 S3P80C5/C80C5/C80C8 Timer 0 Control Register (T0CON) D2H, Set 1, R/W Timer 0 match interrupt pending bit: Timer 0 input clock selection bits: 0 = No interrupt pending 00 = f /4096 0 = Clear pending bit (write)
Page 226 S3P80C5/C80C5/C80C8 BASIC TIMER AND TIMER 0 TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0, Vectors FAH and FCH) The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match interrupt (T0INT). T0OVF is interrupt level IRQ0, vector FAH. T0INT also belongs to interrupt level IRQ0, but is assigned the separate vector address, FCH.
Page 227 BASIC TIMER and TIMER 0 S3P80C5/C80C5/C80C8 Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register.
Page 228 S3P80C5/C80C5/C80C8 BASIC TIMER AND TIMER 0 Bit 1 RESET or Stop Basic Timer Control Register Bits 3,2 (Write '1010xxxxB' to disable) Data Bus Clear 1/4096 RESET 8-Bit Basic Counter 1/1024 (Read-Only) 1/128 Bit 2 Bit 0 Bits 7,6 Data Bus...
Page 229 BASIC TIMER and TIMER 0 S3P80C5/C80C5/C80C8 PROGRAMMING TIP — Configuring the Basic Timer This example shows how to configure the basic timer to sample specifications: 0100H RESET ; Disable all interrupts BTCON,#03H ; Enable the watchdog timer CLKCON,#18H ; Non-divided clock ;...
Page 230 S3P80C5/C80C5/C80C8 BASIC TIMER AND TIMER 0 Programming Tip — Programming Timer 0 This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows: —...
Page 231 BASIC TIMER and TIMER 0 S3P80C5/C80C5/C80C8 PROGRAMMING TIP — Programming Timer 0 (Continued) T0INT PUSH ; Save RP0 to stack ; RP0 ← 60H SRP0 #60H ; R0 ← R0 + 1 ; R2 ← R2 + R0 R2,R0 ; R3 ← R3 + R2 + Carry R3,R2 ;...
Page 232 S3P80C5/C80C5/C80C8 TIMER 1 TIMER 1 OVERVIEW The S3C80C5/C80C8 microcontroller has a 16-bit timer/counter called timer 1 (T1). For universal remote controller applications, timer 1 can be used to generate the envelope pattern for the remote controller signal. Timer 1 has the following components: —...
Page 233 TIMER 1 S3P80C5/C80C5/C80C8 TIMER 1 OVERFLOW INTERRUPT Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the 16-bit up counter. When you set the timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt is generated each time the 16-bit up counter reaches ‘FFFFH’.
Page 234 S3P80C5/C80C5/C80C8 TIMER 1 T1CON.2 T1CON.7-.6 IRQ1 CAOF (T-F/F) T1CON.3 Clear 16-Bit Up-Counter (Read-Only) (note) Match 16-Bit Comparator T1CON.1 T1CON.5-.4 T1CON.0 IRQ1 Timer 1 High/Low Buffer Register T1CON.3 Match Signal T1OVF Timer 1 Data High/Low Register Data Bus NOTES: Match signal is occured only in interval mode.
Page 235 TIMER 1 S3P80C5/C80C5/C80C8 TIMER 1 CONTROL REGISTER (T1CON) The timer 1 control register, T1CON, is located in set 1, FAH, and is read/write addressable. T1CON contains control settings for the following T1 functions: — Timer 1 input clock selection — Timer 1 operating mode selection —...
Page 236 S3P80C5/C80C5/C80C8 TIMER 1 Timer 1 Counter High-Byte Register (T1CNTH) F6H, Set 1, R Reset Value : 00H Timer 1 Counter Low-Byte Register (T1CNTL) F7H, Set 1, R Reset Value : 00H Timer 1 Data High-Byte Register (T1DATAH) F8H, Set 1, R/W...
Page 237 TIMER 1 S3P80C5/C80C5/C80C8 NOTES 11-6...
Page 238 COUNTER A COUNTER A OVERVIEW The S3P80C5/C80C5/C80C8 microcontroller has an 8-bit counter called counter A. Counter A, which can be used to generate the carrier frequency, has the following components (see Figure 12-1): — Counter A control register, CACON — 8-bit down counter with auto-reload function —...
Page 239 COUNTER A S3P80C5/C80C5/C80C8 CACON.6-.7 DIV 1 DIV 2 8-Bit CACON.0 To Other Block Down Counter (CAOF) DIV 4 (P3.1/REM) DIV 8 CACON.3 Repeat Control Interrupt IRQ4 INT.GEN. Control (CAINT) Counter A Data Low Byte Register CACON.2 CACON.4-.5 Counter A Data...
Page 240 S3P80C5/C80C5/C80C8 COUNTER A COUNTER A CONTROL REGISTER (CACON) The counter A control register, CACON, is located in set 1, bank 0, F3H, and is read/write addressable. CACON contains control settings for the following functions (see Figure 12-2): — Counter A clock source selection —...
Page 241 COUNTER A S3P80C5/C80C5/C80C8 Counter A Data High-Byte Register (CADATAH) F4H, Set 1, R/W Reset Value : FFh Counter A Data Low-Byte Register (CADATAL) F5H, Set 1, R/W Reset Value : FFh Figure 12-3. Counter A Registers COUNTER A PULSE WIDTH CALCULATIONS...
Page 242 S3P80C5/C80C5/C80C8 COUNTER A Counter A Clock CAOF = '0' CADATAL = 01-FFH High CADATAH = 001H CAOF = '0' CADATAL = 00H CADATAH = 01-FFH CAOF = '0' CADATAL = 00H CADATAH = 00H CAOF = '1' CADATAL = 00H...
Page 243 COUNTER A S3P80C5/C80C5/C80C8 PROGRAMMING TIP — To Generate 38 kHz, 1/3duty Signal Through P2.1 This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 38 kHz,1/3 Duty carrier frequency. The program parameters are: 8.795 µs...
Page 244 S3P80C5/C80C5/C80C8 COUNTER A PROGRAMMING TIP — To Generate a One Pulse Signal Through P2.1 This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 40 µs width pulse. The program parameters are: 40 µs...
Page 245 COUNTER A S3P80C5/C80C5/C80C8 NOTES 12-8...
Page 246 S3P80C5/C80C5/C80C8 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, S3P80C5/C80C5/C80C8 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in Stop mode —...
Page 247 ELECTRICAL DATA S3P80C5/C80C5/C80C8 Table 13-1. Absolute Maximum Ratings ° = 25 Parameter Symbol Conditions Rating Unit Supply voltage – – 0.3 to + 6.5 Input voltage – – 0.3 to V + 0.3 – 0.3 to V + 0.3 Output voltage...
Page 248 S3P80C5/C80C5/C80C8 ELECTRICAL DATA Table 13-2. D.C. Electrical Characteristics (Continued) ° ° = – 40 C to + 85 C, V = 2.0 V to 3.6 V) Parameter Symbol Conditions Unit Output Low = 2.4 V, I = 12 mA, port °...
Page 249 ELECTRICAL DATA S3P80C5/C80C5/C80C8 Table 13-3. Characteristics of Low Voltage Detect circuit ° ° = – 40 C to + 85 Parameter Symbol Conditions Unit ∆V Hysteresys Voltage of LVD – – (Slew Rate of LVD) Low level detect voltage –...
Page 250 S3P80C5/C80C5/C80C8 ELECTRICAL DATA INTL INTH 0.8 V 0.2 V NOTE: The unit t means one CPU clock period. Figure 13-1. Input Timing for External Interrupts (Port 0) Table 13-7. Oscillation Characteristics ° ° = – 40 C + 85 Oscillator...
Page 251 500 kHz 250 kHz 8.32 kHz 400 kHz Supply Voltage (V) Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) A 1.7 V: 4 MHz b 2.0 V: 8 MHz Figure 13-2. Operating Voltage Range of S3P80C5/C80C5/C80C8...
Page 252 S3P80C5/C80C5/C80C8 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3P80C5/C80C5/C80C8 microcontroller is currently available in a 24-pin SOP and SDIP package. 24-SOP-375 + 0.10 0.15 - 0.05 15.74 MAX 15.34 ± 0.20 0.10 MAX 1.27 (0.69) + 0.10 0.38 - 0.05 NOTE: Dimensions are in millimeters.
Page 253 MECHANICAL DATA S3P80C5/C80C5/C80C8 0-15 24-SDIP-300 23.35 MAX 22.95 ± 0.20 0.46 ± 0.10 1.778 (1.70) 0.89 ± 0.10 NOTE: Dimensions are in millimeters. Figure 14-2. 24-Pin SDIP Package Mechanical Data 14-2...
Page 254 (Person placing the order) (Technical Manager) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) NOTE : Please one more check whether the selected device is S3C80A4/C80A8/C80A5 or S3C80B4/C80B8/C80B5.
Page 256 (Person Placing the Risk Order) (SEC Sales Representative) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) NOTE : Please one more check whether the selected device is S3C80A4/C80A8/C80A5 or S3C80B4/C80B8/C80B5.
Page 258 Other Please describe in detail its application (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) NOTE: Please one more check whether the selected device is S3P80A4/P80A8/P80A5 or S3P80B4/P80B8/P80B5.
Page 260 (Person placing the order) (Technical Manager) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) NOTE: Please one more check whether the selected device is S3P80A4/P80A8/P80A5 or S3P80B4/P80B8/P80B5.
Page 262 Once you choose a read protection, you cannot read again the programming code from the EPROM. OTP Writing will be executed in our manufacturing site. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors occurred from the writing program.
Page 263 BOOK SPINE TEXT SAMSUNG Logo S3P80C5/C80C5/C80C8 Microcontrollers User's Manual, Rev. 1 May 2002...

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