Interrupt Request Register (Irq) - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

5.1.12 INTERRUPT REQUEST REGISTER (IRQ)

You can poll bit values in the interrupt request register, IRQ (DCH, Set1), to monitor interrupt request status for all
levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of same number: bit 0
to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level. A
"1" indicates that an interrupt request has been generated for that level.
IRQ bit values are read-only. You can read (test) the contents of the IRQ register at any time using bit or byte
addressing to determine the current interrupt request status of specific interrupt levels. After a reset, all IRQ status
bits are cleared to "0".
You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing
is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,
however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events
occurred while the interrupt structure was globally disabled.
M S B
In te rru p t R e q u e st R e g iste r (IR Q )
D C H , S e t1 , R e a d-o n ly
.7 .6 .5
IR Q 5
IR Q 6
IR Q 7
Figure 5-9 Interrupt Request Register (IRQ)
.4 .3 .2
IR Q 2
IR Q 3
IR Q 4
In te rru p t le ve l re q u e st p e n d in g b its:
0 = In te rru p t le ve l is n o t p e n d in g
1 = In te rru p t le ve l is p e n d in g
5-12
5 INTERRUPT STRUCTURE
.1 .0 L S B
IR Q 0
IR Q 1