Clock Status During Power-Down Modes; System Clock Control Register (Clkcon) - Samsung S3C9454B User Manual

CLOCK CIRCUIT

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows:
— In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file
and current system register values are retained. Stop mode is released, and the oscillator started, by a reset
operation or by an external interrupt with RC-delay noise filter (for S3C9454B/F9454B, INT0–INT1).
— In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The
current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file is
retained. Idle mode is released by a reset or by an interrupt (external or internally-generated).

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the
following functions:
— Oscillator IRQ wake-up function enable/disable (CLKCON.7)
— Oscillator frequency divide-by value: non-divided, 2, 8, or 16 (CLKCON.4 and CLKCON.3)
The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release
(This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7.
After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the
f /16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU
OSC
clock speed to f , f
OSC OSC
Oscillator IRQ wake-up enable bit:
0 = Enable IRQ for main system
oscillator wake-up function in
power mode.
1 = Disable IRQ for main system
oscillator wake-up function in
power down mode.
7-2
/2 or f /8.
OSC
System Clock Control Register (CLKCON)
MSB .7 .6
Not used for
S3C9454B/F9454B
Figure 7-3. System Clock Control Register (CLKCON)
D4H, R/W
.5 .4 .3 .2
Not used for
S3C9454B/F9454B
Divide-by selection bits for
CPU clock frequency:
00 = fosc/16
01 = fosc/8
10 = fosc/2
11 = fosc (non-divided)
S3C9454B/F9454B
.1 .0 LSB