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S3F84B8_UM_REV 1.00
Timer A operating mode selection bit:
00 = Interval mode (TAOUT mode)
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = PWM mode (OVF interrupt and match
interrupt can occur)
Timer A counter clear bit:
0 = No effect
1 = Clear the timer A counter
NOTE:
Timer A Control Register (TACON)
E4H, Set1, Bank1, R/W, Reset: 00H
MSB
.7
.6
.5
(when write )
Timer A start/stop bit:
0 = Stop timer A
1 = Start timer A
When the counter clear bit(.5) is set, the 8-bit counter is cleared and
it will be cleared automatically.
Figure 11-1
.4
.3
.2
.1
Timer A match Interrupt pending bit:
0 = No pending (clear pending bit when write )
1 = Interrupt pending
Timer A overflow interrupt enable bit :
0 = Disable overflow interrupt
1 = Enable overflow interrrupt
Timer A match/capture interrupt
enable bit:
0 = Disable interrupt
1 = Enable interrrupt
Timer A Control Register (TACON)
11-4
.0
LSB
Timer A OVF Interrupt pending bit:
0 = No pending (clear pending bit when write )
1 = Interrupt pending
11 8-BIT TIMER A
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