Page 1 23-S3-C8248/C8245/P8245/C8247/C8249/P8249-032002 USER'S MANUAL S3C8248/C8245/P8245 /C8247/C8249/P8249 8-Bit CMOS Microcontrollers Revision 3...
Page 2 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: — Efficient register-oriented architecture —...
Page 3 • ROM: 16K-byte (S3C8245/P8245) Basic Timer • RAM: 1056-Byte (S3C8249/P8249, S3C8247) • Overflow signal makes a system reset. • RAM: 544-Byte (S3C8245/P8245, S3C8248) • Watchdog function • Data memory mapped I/O 8-Bit Timer/Counter A Oscillation Sources • Programmable 8-bit timer •...
Page 4 S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW BLOCK DIAGRAM BUZ/P1.4 RESET TAOUT/TAPWM/P3.1 8-Bit TACLK/P3.2 Timer/ Counter A Voltage TACAP/P3.3 VLDREF Detector 8-Bit OSC/ Basic Watch TBPWM/P3.0 Timer/ RESET Voltage Timer Timer Counter B Booster 16-Bit Timer/ Counter 0 VLC0-VLC2 COM0-COM3 T1CAP/P1.0 16-Bit Driver Timer/ I/O Port and Interrupt Control T1CLK/P1.1...
Page 5: Table Of Contents
SEG7 SEG29/P5.5 SEG6 SEG30/P5.6 SEG5 SEG31/P5.7 SEG4 P3.0/TBPWM SEG3 P3.1/TAOUT/TAPWM SEG2 P3.2/TACLK SEG1 P3.3/TACAP/SDAT SEG0 S3C8248/C8245 P3.4/SCLK COM3 COM2 /C8247/C8249 COM1 COM0 (80-QFP-1420C) TEST RESET P0.0/INT0 P0.1/INT1 P0.2/INT2 P2.7/ADC7/V VLDREF P0.3/INT3 P2.6/ADC6 P0.4/INT4 P2.5/ADC5 Figure 1-2. S3C8248/C8245/C8247/C8249 Pin Assignments (80-QFP)
Page 6: Seg26/P5.2
S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW SEG26/P5.2 SEG5 SEG27/P5.3 SEG4 SEG28/P5.4 SEG3 SEG29/P5.5 SEG2 SEG30/P5.6 SEG1 SEG31/P5.7 SEG0 P3.0/TBPWM COM3 P3.1/TAOUT/TAPWM COM2 S3C8248/C8245 P3.2/TACLK COM1 /C8247/C8249 P3.3/TACAP/SDAT COM0 P3.4/SCLK (80-TQFP-1212) TEST P2.7/ADC7/V LDREF RESET P2.6/ADC6 P0.0/INT0 P2.5/ADC5 Figure 1-3. S3C8248/C8245/C8247/C8249 Pin Assignments (80-TQFP)
Page 7 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 PIN DESCRIPTIONS Table 1-1. S3C8248/C8245/C8247/C8249 Pin Descriptions Circuit Share Names Type Description Type (note) Pins Numbers P0.0–P0.7 I/O port with bit programmable pins; D–4 20–27 INT0–INT7 Schmitt trigger input or output mode selected by software; software assignable pull-up.
Page 8 S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW Table 1-1. S3C8248/C8245/C8247/C8249 Pin Descriptions (Continued) Circuit Share Names Type Description Type (note) Pins Numbers ADC0–ADC6 A/D converter analog input channels F–10 36–42 P2.0–P2.6 ADC7 F–18 P2.7 – A/D converter reference voltage – – – A/D converter ground –...
Page 9 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 PIN CIRCUITS Pull-up P-Channel Enable Data Circuit Type C Output Disable RESET) Figure 1-6. Pin Circuit Type D-2 (P3) Figure 1-4. Pin Circuit Type B (RESET Pull-up Data Enable P-Channel Pin Circuit Data Type C Output Disable...
Page 10 S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW Open drain Pull-up Enable Pull-up Resistor Enable P-CH Data Circuit Data Output Type C Disable N-CH ADC & VLD Output Enable Disable Data Schmitt Trigger To ADC Figure 1-8. Pin Circuit Type E-2 (P1) Figure 1-10. Pin Circuit Type F-18 (P2.7/VLD...
Page 11 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 Output Disable Figure 1-12. Pin Circuit Type H-4 Open Drain EN Pull-up Enable Data LCD Out EN Circuit Type H-4 Output Disable Figure 1-13. Pin Circuit Type H-14 (P4, P5) 1-10...
Page 12 A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3C8248/C8245 has an internal 16-Kbyte mask-programmable ROM. The S3C8247/C8249 has an internal 32-Kbyte mask-programmable ROM.
Page 13 ADDRESS SPACES S3C8248/C8245/P8245/C8247/C8249/P8249 PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3C8248 has 8K bytes internal mask- programmable program memory, the S3C8245 has 16K bytes, the S3C8247 has 24K bytes and the S3C8249 has 32K bytes.
Page 14 ADDRESS SPACES REGISTER ARCHITECTURE In the S3C8248/C8245/C8247/C8249 implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area.
Page 15 Data Registers (All Addressing Modes) Bytes (All addressing modes) LCD Display Reigster NOTE: In case of S3C8248/C8245/P8245, there are page 0, page 1, and page 2. Page 2 is for LCD display register, 16 bytes. Figure 2-2. Internal Register File Organization...
Page 16 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C8248/C8245/C8247/C8249 microcontroller, a paged register file expansion is implemented for LCD data registers, and the register page pointer must be changed to address other pages.
Page 17 2 address range (C0H–FFH) is accessible on pages 0–3. S3C8248/C8245, the set 2 address range (C0H-FFH) is accessible on pages 0-1. The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only Register addressing mode to access set 1 locations.
Page 18 ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3C8248/C8245/C8247/C8249's four or two 256-byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset.
Page 19 ADDRESS SPACES S3C8248/C8245/P8245/C8247/C8249/P8249 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices."...
Page 20 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESS SPACES USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
Page 21 ADDRESS SPACES S3C8248/C8245/P8245/C8247/C8249/P8249 F7H (R7) 8-Byte Slice F0H (R0) 16-Byte Register File Contiguous Contains 32 1 1 1 1 0 X X X working 8-Byte Slices Register block 7H (R15) 0 0 0 0 0 X X X 8-Byte Slice 0H (R0) Figure 2-7.
Page 22 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESS SPACES REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2.
Page 23 C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area). LCD Data NOTE: In the S3C8248/C8245/C8247/C8249 Registers microcontroller, pages 0-4 are implemented. Pages 0-4 contain all of the addressable registers in the internal register file.
Page 24 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area.
Page 25 ADDRESS SPACES S3C8248/C8245/P8245/C8247/C8249/P8249 PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Examples 1. LD 0C2H,40H ; Invalid addressing mode!
Page 26 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESS SPACES Selects RP0 or RP1 Address OPCODE 4-bit address Register pointer provides three provides five low-order bits high-order bits Together they create an 8-bit register address Figure 2-11. 4-Bit Working Register Addressing 0 1 1 1 0 0 0 0...
Page 27 ADDRESS SPACES S3C8248/C8245/P8245/C8247/C8249/P8249 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B."...
Page 28 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESS SPACES 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 Selects RP1 8-bit address Register form instruction 1 1 0 0 0 1 1 1 0 1 0 1 0 1 1...
Page 29 SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C8248/C8245/C8247/C8249, the SPL must be initialized to an 8-bit value in the range 00H–FFH. The SPH register is not needed and can be used as a general- purpose register, if necessary.
Page 30 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESS SPACES PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SPL ← FFH SPL,#0FFH ; (Normally, the SPL is set to 0FFH by the initialization ;...
Page 31 ADDRESS SPACES S3C8248/C8245/P8245/C8247/C8249/P8249 NOTES 2-20...
Page 32 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.
Page 33 ADDRESSING MODES S3C8248/C8245/P8245/C8247/C8249/P8249 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Page 34 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
Page 35 ADDRESSING MODES S3C8248/C8245/P8245/C8247/C8249/P8249 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory REGISTER Example PAIR Instruction Points to References OPCODE Register Pair Program 16-Bit Memory Address Points to Program Program Memory Memory Sample Instructions: Value used in OPERAND Instruction CALL...
Page 36 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points Program Memory to start fo working register 4-bit block 3 LSBs Working Register Point to the OPCODE ADDRESS...
Page 37 ADDRESSING MODES S3C8248/C8245/P8245/C8247/C8249/P8249 INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register 4-bit Working block Register Address Register Next 2-bit Point Pair OPCODE...
Page 38 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
Page 39 ADDRESSING MODES S3C8248/C8245/P8245/C8247/C8249/P8249 INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register block OFFSET NEXT 2 Bits 4-bit Working dst/src Register Register Address Point to Working...
Page 40 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of Program Memory working register OFFSET block OFFSET NEXT 2 Bits 4-bit Working dst/src Register Register Address...
Page 41 ADDRESSING MODES S3C8248/C8245/P8245/C8247/C8249/P8249 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
Page 42 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16-bit immediate address CALL DISPLAY Where DISPLAY is a 16-bit immediate address Figure 3-11.
Page 43 ADDRESSING MODES S3C8248/C8245/P8245/C8247/C8249/P8249 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Page 44 S3C8248/C8245/P8245/C8247/C8249/P8249 ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.
Page 45 ADDRESSING MODES S3C8248/C8245/P8245/C8247/C8249/P8249 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used.
Page 46 CONTROL REGISTERS OVERVIEW In this chapter, detailed descriptions of the S3C8248/C8245/C8247/C8249 control registers are presented in an easy-to-read format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.
Page 47 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 Table 4-2. Set 1, Bank 0 Registers Register Name Mnemonic Decimal Port 0 control High register P0CONH Port 0 control Low register P0CONL Port 0 interrupt control register P0INT Port 0 interrupt pending register P0PND Port 1 control High register...
Page 48 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER Table 4-3. Set 1, Bank 1 Registers Register Name Mnemonic Decimal Locations E0H–EBH is not mapped. Port 4 control High register P4CONH Port 4 control Low register P4CONL Port 5 control High register P5CONH Port 5 control Low register P5CONL Locations F0H is factory use only.
Page 49 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 Bit number(s) that is/are appended to Name of individual the register name for bit addressing bit or related bits Register location in the internal Register address register file Register ID Register name (hexadecimal) FLAGS − − System Flags Register...
Page 50 — A/D Converter Control Register Set 1, Bank 1 Bit Identifier RESET RESET Value – Read/Write – Addressing Mode Register addressing mode only Not used for the S3C8248/C8245/C8247/C8249 .6–.4 A/D Input Pin Selection Bits ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6...
Page 51 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 BTCON — Basic Timer Control Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.4 Watchdog Timer Function Disable Code (for System Reset) Disable watchdog timer function Others Enable watchdog timer function .3–.2...
Page 52 – – – – – – Addressing Mode Register addressing mode only .7–.5 Not used for the S3C8248/C8245/C8247/C8249 (note) .4–.3 CPU Clock (System Clock) Selection Bits fxx/16 fxx/8 fxx/2 .2–.0 Not used for the S3C8248/C8245/C8247/C8249 NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load...
Page 53 — External Memory Timing Register Set 1, Bank 0 Bit Identifier RESET Value RESET – – – – – – – Read/Write – – – – – – – – Addressing Mode Register addressing mode only .7–.0 Not used for the S3C8248/C8245/C8247/C8249...
Page 54 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER FLAGS — System Flags Register Set 1 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only Carry Flag (C) Operation does not generate a carry or borrow condition Operation generates a carry-out or borrow into high-order bit 7...
Page 55 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 — Interrupt Mask Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.4–0.7 Disable (mask) Enable (unmask) Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.0–0.3...
Page 56 – Addressing Mode Register addressing mode only .7–.3 Not used for the S3C8248/C8245/C8247/C8249 Timer 1 Overflow Interrupt Pending Bit Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending Timer 1 Match/Capture Interrupt Pending Bit...
Page 57 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 — Instruction Pointer (High Byte) Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8).
Page 58 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER — Interrupt Priority Register Set 1, Bank 0 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C Group priority undefined B >...
Page 59 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 — Interrupt Request Register Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.4–0.7 Not pending Pending Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.0–0.3...
Page 60 LCD Output Segment and Pin Configuration Bits P4.0–P4.3 I/O is selected SEG16–SEG19 is selected, P4.0–P4.3 I/O is disabled Not used for the S3C8248/C8245/C8247/C8249 LCD Bias Voltage Selection Bit Enable LCD initial circuit (internal bias voltage) Disable LCD initial circuit for external LCD driving resister (external bias...
Page 61 Read/Write – – Addressing Mode Register addressing mode only .7–.6 Not used for the S3C8248/C8245/C8247/C8249 .5–.4 LCD Clock (LCDCK) Frequency Selection Bits 32.768 kHz watch timer clock (fw)/2 = 64 Hz 32.768 kHz watch timer clock (fw)/2 = 128 Hz 32.768 kHz watch timer clock (fw)/2...
Page 62 – – – Addressing Mode Register addressing mode only .7–.5 Not used for the S3C8248/C8245/C8247/C8249 Sub-system Oscillator Driving Ability Control Bit Strong driving ability Normal driving ability Main System Oscillator Control Bit Main System Oscillator RUN Main System Oscillator STOP...
Page 63 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 P0CONH — Port 0 Control Register (High Byte) Set 1,Bank 0 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P0.7/INT7 Schmitt trigger input mode; pull-up ; interrupt on falling edge Schmitt trigger input mode; interrupt on rising edge Schmitt trigger input mode;...
Page 64 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER P0CONL — Port 0 Control Register (Low Byte) Set 1, Bank 0 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P0.3/INT3 Schmitt trigger input mode; pull-up ; interrupt on falling edge Schmitt trigger input mode; interrupt on rising edge Schmitt trigger input mode;...
Page 65 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 P0INT — Port 0 Interrupt Control Register Set 1, Bank 0 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only P0.7 External Interrupt (INT7) Enable Bit Disable interrupt Enable interrupt P0.6 External Interrupt (INT6) Enable Bit...
Page 66 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER P0PND — Port 0 Interrupt Pending Register Set 1, Bank 0 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only P0.7/INT7 Interrupt Pending Bit Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending P0.6/INT6 Interrupt Pending Bit...
Page 67 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 P1CONH — Port 1 Control Register (High Byte) Set 1, Bank 0 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P1.7/SI Input mode (SI) Output mode, open-drain Alternative function (push-pull output) Output mode, push-pull .5–.4...
Page 68 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER P1CONL — Port 1 Control Register (Low Byte) Set 1, Bank 0 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P1.3 Input mode Output mode, open-drain Alternative function (push-pull output mode) Output mode, push-pull .5–.4...
Page 69 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 P1PUP — Port 1 Pull-up Control Register Set 1, Bank 0 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only P1.7 Pull-up Resistor Enable Bit Pull-up disable Pull-up enable P1.6 Pull-up Resistor Enable Bit...
Page 70 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER P2CONH — Port 2 Control Register (High Byte) Set 1, Bank 0 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P2.7/VLDREF/ADC7 Input mode Input mode, pull-up Alternative function (ADC & VLD mode) Output mode, push-pull .5-.4...
Page 71 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 P2CONL — Port 2 Control Register (Low Byte) Set 1, Bank 0 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P2.3/ADC3 Input mode Input mode, pull-up Alternative function (ADC mode) Output mode, push-pull .5–.4...
Page 72 Set 1, Bank 0 Bit Identifier RESET RESET Value Read/Write – – – – – – Addressing Mode Register addressing mode only .7–.2 Not used for the S3C8248/C8245/C8247/C8249 .1–.0 P3.4 Mode Selection Bits Input mode Input mode, pull-up Output mode, push-pull 4-27...
Page 73 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 P3CONL — Port 3 Control Register (Low Byte) Set 1, Bank 0 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P3.3/TACAP Mode Selection Bits Input mode (TACAP) Input mode, pull-up (TACAP) Output mode, push-pull Output mode, push-pull .5–.4...
Page 74 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER P4CONH — Port 4 Control Register (High Byte) Set 1, Bank 1 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P4.7/SEG23 Mode Selection Bits Input mode Input mode, pull-up Open-drain output mode Push-pull output mode .5–.4...
Page 75 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 P4CONL — Port 4 Control Register (Low Byte) Set 1, Bank 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P4.3/SEG19 Mode Selection Bits Input mode Input mode, pull-up Open-drain output mode Push-pull output mode .5–.4...
Page 76 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER P5CONH — Port 5 Control Register (High Byte) Set 1, Bank 1 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P5.7/SEG31 Mode Selection Bits Input mode Input mode, pull-up Open-drain output mode Push-pull output mode .5–.4...
Page 77 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 P5CONL — Port 5 Control Register (Low Byte) Set 1, Bank 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 P5.3/SEG27 Mode Selection Bits Input mode Input mode, pull-up Open-drain output mode Push-pull output mode .5–.4...
Page 78 The pages 0-3 are used for general purpose register file, and page 4 is used for LCD data register or general purpose registers. In case of S3C8248/C8245, pages 0-1 are used for general purpose and page 2 is used for LCD data register or general purpose registers.
Page 79 8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H–C7H. .2–.0 Not used for the S3C8248/C8245/C8247/C8249 — Register Pointer 1 Set 1 Bit Identifier...
Page 80 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER SIOCON — SIO Control Register Set 1, Bank 0 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only SIO Shift Clock Selection Bit Internal clock (P.S clock) External clock (SCK) Data Direction Control Bit...
Page 81 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 — Stack Pointer (High Byte) Set 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.0 Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15–SP8).
Page 82 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER STPCON — Stop Control Register Set 1, Bank 0 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only .7–.0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instruction NOTE: Before execute the STOP instruction, You must set this STPCON register as “10100101b”.
Page 83 RESET Value RESET – – Read/Write – – Addressing Mode Register addressing mode only Not used, But you must keep "0" .6–.5 Not used for the S3C8248/C8245/C8247/C8249 .4–.2 Fast Interrupt Level Selection Bits IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7...
Page 84 Timer 0 Input Clock Selection Bits TBOF (T-FF) fxx/256 fxx/64 fxx/8 Timer 0 Operating Mode Selection Bits Not used for the S3C8248/C8245/C8247/C8249 Timer 0 Counter Clear Bit No effect Clear the timer 0 counter (when write) Timer 0 Counter Enable Bit Disable counting operation...
Page 85 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 T1CON — Timer 1 Control Register Set 1, Bank 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.5 Timer 1 Input Clock Selection Bits fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 External clock (T1CLK) falling edge...
Page 86 S3C8248/C8245/P8245/C8247/C8249/P8249 CONTROL REGISTER TACON — Timer A Control Register Set 1, Bank 0 Bit Identifier RESET RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 Timer A Input Clock Selection Bits fxx/1024 fxx/256 fxx/64 External clock (TACLK) .5–.4 Timer A Operating Mode Selection Bits...
Page 87 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 TBCON — Timer B Control Register Set 1, Bank 0 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only .7–.6 Timer B Input Clock Selection Bits fxx/2 fxx/4 fxx/8 .5–.4 Timer B Interrupt Time Selection Bits...
Page 88 RESET RESET Value Read/Write – – – Addressing Mode Register addressing mode only .7–.5 Not used for the S3C8248/C8245/C8247/C8249 Source Bit Internal source External source VLD Output Bit > V (when VLD is enabled) < V (when VLD is enabled)
Page 89 CONTROL REGISTERS S3C8248/C8245/P8245/C8247/C8249/P8249 WTCON — Watch Timer Control Register Set 1, Bank 1 Bit Identifier RESET Value RESET Read/Write Addressing Mode Register addressing mode only Watch Timer Clock Selection Bit Main system clock divided by 2 (fxx/128) Sub system clock (fxt)
Page 90 Sources A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow. Each vector can have several interrupt sources. In the S3C8248/C8245/C8247/C8249 interrupt structure, there are sixteen possible interrupt sources. When a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually"...
Page 91 – S Type 3: One level (IRQn) + multiple vectors (V – V ) + multiple sources (S – S – S In the S3C8248/C8245/C8247/C8249 microcontroller, two interrupt types are implemented. Levels Vectors Sources Type 1: IRQn Type 2: IRQn...
Page 92 INTERRUPT STRUCTURE S3C8248/C8245/C8247/C8249 INTERRUPT STRUCTURE The S3C8248/C8245/C8247/C8249 microcontroller supports sixteen interrupt sources. All sixteen of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.
Page 93 S3C8248/C8245/P8245/C8247/C8249/P8249 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8248/C8245/C8247/C8249 interrupt structure are stored in the vector address area of the internal 32-Kbyte ROM, 0H–7FFFH, or 8, 16, 24-Kbyte (see Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
Page 94 S3C8248/C8245/P8245/C8247/C8249/P8249 INTERRUPT STRUCTURE Table 5-1. Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Interrupt Priority in Value Value Level Level RESET √ 100H Basic timer overflow – √ √ Timer A overflow IRQ0 √ √ Timer A match/capture √...
Page 95 Interrupt priority register Controls the relative processing priorities of the interrupt levels. The seven levels of S3C8248/C8245/C8247/C8249 are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.
Page 96 S3C8248/C8245/P8245/C8247/C8249/P8249 INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are: — Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 ) —...
Page 97 INTERRUPT STRUCTURE S3C8248/C8245/P8245/C8247/C8249/P8249 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers...
Page 98 EI and DI instructions for this purpose. System Mode Register (SYM) DEH, Set 1, R/W Global interrupt enable bit: Not used for the S3C8248/C8245/C8247/C8249 0 = Disable all interrupts processing 1 = Enable all interrupts processing Fast interrupt level selection bits:...
Page 99 INTERRUPT STRUCTURE S3C8248/C8245/P8245/C8247/C8249/P8249 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
Page 100 S3C8248/C8245/P8245/C8247/C8249/P8249 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
Page 101 INTERRUPT STRUCTURE S3C8248/C8245/P8245/C8247/C8249/P8249 Interrupt Priority Register (IPR) FEH, Set 1, Bank 0, R/W Group priority: Group A 0 = IRQ0 > IRQ1 D7 D4 D1 1 = IRQ1 > IRQ0 Group B 0 0 0 = Undefined 0 = IRQ2 > (IRQ3, IRQ4) 0 0 1 = B >...
Page 102 S3C8248/C8245/P8245/C8247/C8249/P8249 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on.
Page 103 "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software. In the S3C8248/C8245/C8247/C8249 interrupt structure, the timer 0 overflow interrupt (IRQ0) belongs to this category of interrupts in which pending condition is cleared automatically by hardware.
Page 104 S3C8248/C8245/P8245/C8247/C8249/P8249 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source.
Page 105 INTERRUPT STRUCTURE S3C8248/C8245/P8245/C8247/C8249/P8249 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack.
Page 106 — When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' (“FLAGS prime”). NOTE For the S3C8248/C8245/C8247/C8249 microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–IRQ7, can be selected for fast interrupt processing. Procedure for Initiating Fast Interrupts To initiate fast interrupt processing, follow these steps: 1.
Page 107 INTERRUPT STRUCTURE S3C8248/C8245/P8245/C8247/C8249/P8249 NOTES 5-18...
Page 108 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: —...
Page 109 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst,src Load dst,src Load bit dst,src Load external data memory dst,src Load program memory LDED dst,src Load external data memory and decrement LDCD dst,src Load program memory and decrement...
Page 110 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions dst,src Add with carry dst,src dst,src Compare Decimal adjust Decrement DECW Decrement word dst,src Divide Increment INCW Increment word MULT dst,src Multiply dst,src Subtract with carry...
Page 111 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL Call procedure CPIJE dst,src Compare, increment and jump on equal...
Page 112 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic SWAP Swap nibbles CPU Control Instructions Complement carry flag...
Page 113 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic.
Page 114 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET FLAG DESCRIPTIONS Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.
Page 115 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation –...
Page 116 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Bit (b) of working register Rn.b (n = 0–15, b = 0–7) Bit 0 (LSB) of working register Rn (n = 0–15)
Page 117 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1.b, R2 BXOR r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb SRP/0/1 BTJR IRR1 r1,r2 r1,Ir2 R2,R1...
Page 118 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – DJNZ NEXT r1,R2 r2,R1 r1,RA cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ ↓ ENTER EXIT IDLE ↓ ↓ ↓ ↓ ↓ ↓ ↓...
Page 119 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"...
Page 120 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...
Page 121 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Add with carry dst,src dst ← dst + src + c Operation: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed.
Page 122 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
Page 123 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...
Page 124 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET BAND — Bit AND BAND dst,src.b BAND dst.b,src dst(0) ← dst(0) AND src(b) Operation: dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source).
Page 125 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Bit Compare dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.
Page 126 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET BITC — Bit Complement BITC dst.b dst(b) ← NOT dst(b) Operation: This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
Page 127 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 BITR — Bit Reset BITR dst.b dst(b) ← 0 Operation: The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode...
Page 128 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET BITS — Bit Set BITS dst.b dst(b) ← 1 Operation: The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode...
Page 129 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Bit OR dst,src.b dst.b,src dst(0) ← dst(0) OR src(b) Operation: dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination.
Page 130 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b If src(b) is a "0", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...
Page 131 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b If src(b) is a "1", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...
Page 132 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src dst(0) ← dst(0) XOR src(b) Operation: dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected.
Page 133 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 CALL — Call Procedure CALL ← Operation: SP – 1 ← ← SP –1 ← ← The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
Page 134 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
Page 135 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Clear dst ← "0" Operation: The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: →...
Page 136 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
Page 137 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Compare dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Page 138 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA If dst – src = "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter.
Page 139 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA If dst – src "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement...
Page 140 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Decimal Adjust dst ← DA dst Operation: The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not...
Page 141 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Decimal Adjust (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH R1,R0 R1 ←...
Page 142 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise.
Page 143 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 DECW — Decrement Word DECW dst ← dst – 1 Operation: The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one.
Page 144 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Disable Interrupts SYM (0) ← 0 Operation: Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
Page 145 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Divide (Unsigned) dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination.
Page 146 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst r ← r – 1 Operation: If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.
Page 147 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Enable Interrupts SYM (0) ← 1 Operation: An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
Page 148 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET ENTER — Enter ENTER ← Operation: SP – 2 ← ← ← ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer.
Page 149 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 EXIT — Exit EXIT ← Operation: ← SP + 2 ← ← IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.
Page 150 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected.
Page 151 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.
Page 152 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET INCW — Increment Word INCW dst ← dst + 1 Operation: The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.
Page 153 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) FLAGS ← @SP PC ↔ IP Operation: SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine.
Page 154 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.
Page 155 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...
Page 156 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc...
Page 157 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Load (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0,#10H R0 = 10H →...
Page 158 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Load Bit dst,src.b dst.b,src dst(0) ← src(b) Operation: dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected.
Page 159 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 LDC/LDE — Load Memory LDC/LDE dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory.
Page 160 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: ;...
Page 161 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
Page 162 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
Page 163 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src rr ← rr – 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented.
Page 164 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src rr ← rr + 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented.
Page 165 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Load Word dst,src dst ← src Operation: The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode...
Page 166 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET MULT — Multiply (Unsigned) MULT dst,src dst ← dst × src Operation: The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.
Page 167 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 NEXT — Next NEXT PC ← @ IP Operation: IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.
Page 168 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected.
Page 169 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...
Page 170 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.
Page 171 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 POPUD — Pop User Stack (Decrementing) POPUD dst,src dst ← src Operation: IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.
Page 172 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET POPUI — Pop User Stack (Incrementing) POPUI dst,src dst ← src Operation: IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.
Page 173 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 PUSH — Push To Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.
Page 174 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src IR ← IR – 1 Operation: dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.
Page 175 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src IR ← IR + 1 Operation: dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.
Page 176 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
Page 177 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
Page 178 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
Page 179 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Rotate Left Through Carry dst (0) ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...
Page 180 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
Page 181 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Rotate Right Through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...
Page 182 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Select Bank 0 BANK ← 0 Operation: The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file.
Page 183 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Select Bank 1 BANK ← 1 Operation: The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3C8-series microcontrollers.)
Page 184 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Subtract with Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
Page 185 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex)
Page 186 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.
Page 187 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 SRP/SRP0/SRP1 — Set Register Pointer SRP0 SRP1 ← Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) src (3–7) ← If src (1) = 0 and src (0) = 1 then: RP1 (3–7) src (3–7)
Page 188 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.
Page 189 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
Page 190 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET SWAP — Swap Nibbles SWAP dst (0 – 3) ↔ dst (4 – 7) Operation: The contents of the lower four bits and upper four bits of the destination operand are swapped. Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise.
Page 191 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Test Complement Under Mask dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
Page 192 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.
Page 193 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 — Wait for Interrupt Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt .
Page 194 S3C8248/C8245/P8245/C8247/C8249/P8249 INSTRUCTION SET — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...
Page 195 INSTRUCTION SET S3C8248/C8245/P8245/C8247/C8249/P8249 NOTES 6-88...
Page 196 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the S3C8248/C8245/C8247/C8249 by an external crystal can range from 1 MHz to 10 MHz. The maximum CPU clock frequency is 10 MHz. The X and X pins connect the external oscillator or clock source to the on-chip clock circuit.
Page 197 CLOCK CIRCUIT S3C8248/C8245/P8245/C8247/C8249/P8249 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset operation or an external interrupt (with RC delay noise filter), and can be released by internal interrupt too when the sub-system oscillator is running and watch timer is operating with sub-system clock.
Page 198 S3C8248/C8245/P8245/C8247/C8249/P8249 CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in the bank 0 of set 1, address D4H. It is read/write addressable and has the following functions: — Oscillator frequency divide-by value After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.
Page 199 CLOCK CIRCUIT S3C8248/C8245/P8245/C8247/C8249/P8249 Oscillator Control Register (OSCCON) F3H, Set 1, bank 0, R/W Not used Not used System clock selection bit: 0 = Main oscillator select 1 = Subsystem oscillator select Subsystem oscillator driving Subsystem oscillator control bit: ability control bit:...
Page 200 RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings the S3C8248/C8245/C8247/C8249 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance.
Page 201 RESET and POWER-DOWN S3C8248/C8245/P8245/C8247/C8249/P8249 HARDWARE RESET VALUES Table 8-1, 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: —...
Page 202 RESET S3C8248/C8245/P8245/C8247/C8249/P8249 and POWER-DOWN Table 8-2. KS88C2416/P2416 Set 1, Bank 0 Register Values after RESET RESET Bit Values after R R ESET ESET Register Name Mnemonic Address Port 0 Control High Register P0CONH Port 0 Control Low Register P0CONL Port 0 interrupt Control Register...
Page 203 RESET and POWER-DOWN S3C8248/C8245/P8245/C8247/C8249/P8249 Table 8-3. S3C8245/P8245 Set 1, Bank 1 Register Values after RESET RESET Bit Values after R R ESET ESET Register Name Mnemonic Address Port 4 control High register P4CONH Port 4 control Low register P4CONL Port 5 Control High Register...
Page 204 External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller’s current internal operating mode. The external interrupts in the S3C8248/C8245/C8247/C8249 interrupt structure that can be used to release Stop mode are: —...
Page 205 RESET and POWER-DOWN S3C8248/C8245/P8245/C8247/C8249/P8249 IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals timers remain active.
Page 206 The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. Table 9-1 gives you a general overview of the S3C8248/C8245/C8247/C8249 I/O port functions. Table 9-1. S3C8248/C8245/C8247/C8249 Port Configuration Overview...
Page 207 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all four S3C8248/C8245/C8247/C8249 I/O port data registers. Data registers for ports 0, 1, 2, 3, 4, and 5 have the general format shown in Figure 9-1.
Page 208 S3C8248/C8245/P8245/C8247/C8249/P8249 I/O PORTS PORT 0 Port 0 is an 8-bit I/O Port that you can use two ways: — General-purpose I/O — External interrupt inputs for INT0–INT7 Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location F6H in set 1, bank 0.
Page 209 I/O PORTS S3C8248/C8245/P8245/C8247/C8249/P8249 Port 0 Control Register, High Byte (P0CONH) E0H, Set 1, Bank 0, R/W P0.7 P0.6 P0.5 P0.4 (INT7) (INT6) (INT5) (INT4) P0CONH bit-pair pin configuration Schmitt trigger input mode, pull-up, interrupt on falling edge Schmitt trigger input mode, interrupt on rising edge...
Page 210 S3C8248/C8245/P8245/C8247/C8249/P8249 I/O PORTS Port 0 Interrupt Control Register (P0INT) E2H, Set 1, Bank 0, R/W INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 P0INT bit configuration settings: Interrupt Disable Interrupt Enable Figure 9-3. Port 0 Interrupt Control Register (P0INT) Port 0 Interrupt Pending Register (P0PND)
Page 211 I/O PORTS S3C8248/C8245/P8245/C8247/C8249/P8249 PORT 1 Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location F7H in set 1, bank 0. P1.0–P1.7 can serve inputs, as outputs (push pull or open-drain) or you can configure the following alternative functions: —...
Page 212 S3C8248/C8245/P8245/C8247/C8249/P8249 I/O PORTS Port 1 Control Register, Low Byte E5H, Set 1, Bank 0, R/W P1.0/T1CAP P1.1/T1CLK P1.2/T1OUT /T1PWM P1.3 P1CONL bit-pair pin configuration settings Input mode (T1CAP, T1CLK) Output mode, open-drain Alternative function (T1OUT, T1PWM, other pins are push-pull...
Page 213 I/O PORTS S3C8248/C8245/P8245/C8247/C8249/P8249 PORT 2 Port 2 is an 8-bit I/O port that can be used for general-purpose I/O as A/D converter inputs, ADC0–ADC7. The pins are accessed directly by writing or reading the port 2 data register, P2 at location F8H in set 1, bank 0.
Page 214 S3C8248/C8245/P8245/C8247/C8249/P8249 I/O PORTS Port 2 Control Register,Low Byte (P2CONL) E7H, Set 1, Bank 0, R/W P2.0 (ADC0) P2.1 (ADC1) P2.2 (ADC2) P2.3 (ADC3) P2CONL bit-pair pin configuration Input mode Input mode, pull-up Alternative function (ADC mode) Output mode, push-pull NOTE: If a pin is enabled for ADC mode by ADCEN, normal I/O and pull-up resistance are disabled.
Page 215 I/O PORTS S3C8248/C8245/P8245/C8247/C8249/P8249 PORT 3 Port 3 is an 5-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location F9H in set 1, bank 0. P3.0–P3.3 can serve as inputs (with or without pull-ups), as push-pull outputs, or you can configure the following alternative functions: —...
Page 216 S3C8248/C8245/P8245/C8247/C8249/P8249 I/O PORTS Port 3 Control Low Register (P3CONL) E9H, Set 1, Bank 0, R/W P3.0/TBPWM P3.1/TAOUT/ P3.2/TACLK TAPWM P3.3/TACAP P3CONL bit-pair pin configuration settings Input mode (TACAP, TACLK) Input mode, pull-up (TACAP) Alternative function (TAOUT,TAPWM, TBPWM P3.2, P3.3 is push-pull output mode) Output mode, push-pull Figure 9-11.
Page 217 I/O PORTS S3C8248/C8245/P8245/C8247/C8249/P8249 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location FAH in set 1, bank 0. P4.0–P4.7 can serve as inputs (with or without pull-ups), as output (open drain or push-pull).
Page 218 S3C8248/C8245/P8245/C8247/C8249/P8249 I/O PORTS Port 4 Control Register, Low Byte EDH, Set 1, Bank 1, R/W P4.0/SEG16 P4.1/SEG17 P4.2/SEG18 P4.3/SEG19 P4CONL bit-pair pin configuration settings Input mode Input mode, pull-up Opendrain output mode Output mode, push-pull NOTE: If LCD is enabled by LCON.4, SEG signal go out otherwise port 4 I/0 can be selected.
Page 219: Seg30/P5.6
I/O PORTS S3C8248/C8245/P8245/C8247/C8249/P8249 PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location FBH in set 1, bank 0. P5.0–P5.7 can serve as inputs (with without pull-ups), as output (open drain or push-pull).
Page 220 S3C8248/C8245/P8245/C8247/C8249/P8249 I/O PORTS Port 5 Control Register, Low Byte EFH, Set 1, Bank 1, R/W P5.0/SEG24 P5.1/SEG25 P5.2/SEG26 P5.3/SEG27 P5CONL bit-pair pin configuration settings Input mode Input mode, pull-up Opendrain output mode Output mode, push-pull NOTE: If LCD is enabled by LCON.6, SEG signal go out otherwise port 5 I/0 can be selected.
Page 221 I/O PORTS S3C8248/C8245/P8245/C8247/C8249/P8249 NOTES 9-16...
Page 222 BASIC TIMER BASIC TIMER OVERVIEW S3C8248/C8245/C8247/C8249 has an 8-bit basic timer . BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or —...
Page 223 BASIC TIMER S3C8248/C8245/P8245/C8247/C8249/P8249 Basic TImer Control Register (BTCON) D3H, Set 1, R/W Divider clear bit: Watchdog timer enable bits: 0 = No effect 1010B = Disable watchdog function 1= Clear dvider Other value = Enable watchdog function Basic timer counter clear bit:...
Page 224 S3C8248/C8245/P8245/C8247/C8249/P8249 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function.
Page 225 BASIC TIMER S3C8248/C8245/P8245/C8247/C8249/P8249 RESET or STOP Bit 1 Bits 3, 2 Basic Timer Control Register (Write '1010xxxxB' to Disable) Data Bus /4096 Clear /1024 8-Bit Up Counter /128 (BTCNT, Read-Only) RESET (NOTE) Start the CPU Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
Page 226 S3C8248/C8245/P8245/C8247/C8249/P8249 8-BIT TIMER A/B 8-BIT TIMER A/B 8-BIT TIMER A OVERVIEW The 8-bit timer A is an 8-bit general-purpose timer/counter. Timer A has three operating modes, one of which you select using the appropriate TACON setting: — Interval timer mode (Toggle output at TAOUT pin) —...
Page 227 8-BIT TIMER A/B S3C8248/C8245/P8245/C8247/C8249/P8249 FUNCTION DESCRIPTION Timer A Interrupts (IRQ0, Vectors E0H and E2H) The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/ capture interrupt (TAINT). TAOVF is interrupt level IRQ0, vector E2H. TAINT also belongs to interrupt level IRQ0, but is assigned the separate vector address, E0H.
Page 228 S3C8248/C8245/P8245/C8247/C8249/P8249 8-BIT TIMER A/B TIMER A CONTROL REGISTER (TACON) You use the timer A control register, TACON, to — Select the timer A operating mode (interval timer, capture mode, or PWM mode) — Select the timer A input clock frequency —...
Page 229 8-BIT TIMER A/B S3C8248/C8245/P8245/C8247/C8249/P8249 BLOCK DIAGRAM TACON.2 TAOVF Overflow Pending TACON.7-.6 Data Bus TACON.3 /1024 /256 Clear TACON.1 8-bit Up-Counter (Read Only) TACLK TAINT Match 8-bit Comparator TACON.0 TACAP Pending Timer A Buffer Reg TAOUT TAPWM TACON.5.4 TACON.5.4 Timer A Data Register...
Page 230: P3.0/Tbpwm
8-BIT TIMER B OVERVIEW The S3C8248/C8245/P8245 micro-controller has an 8-bit counter called timer B. Timer B, which can be used to generate the carrier frequency of a remote controller signal. Pending condition of timer B is cleared automatically by hardware.
Page 231 8-BIT TIMER A/B S3C8248/C8245/P8245/C8247/C8249/P8249 Timer B Control Register ECH, Set 1, Bank 0, R/W Timer B input clock selection bits: Timer B output flip-flop control bit: 00 = fxx 0 = TBOF is low 01 = fxx/2 1 = TBOF is high...
Page 232 S3C8248/C8245/P8245/C8247/C8249/P8249 8-BIT TIMER A/B TIMER B PULSE WIDTH CALCULATIONS HIGH To generate the above repeated waveform consisted of low period time, t , and high period time, t HIGH When TBOF = 0, = (TBDATAL + 2) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock.
Page 233 8-BIT TIMER A/B S3C8248/C8245/P8245/C8247/C8249/P8249 Timer B Clock TBOF = '0' TBDATAL = 01-FFH TBDATAH = 00H TBOF = '0' High TBDATAL = 00H TBDATAH = 01-FFH TBOF = '0' TBDATAL = 00H TBDATAH = 00H TBOF = '1' High TBDATAL = 00H...
Page 234 S3C8248/C8245/P8245/C8247/C8249/P8249 8-BIT TIMER A/B PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.0 This example sets Timer B to the repeat mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 38 kHz,1/3 Duty carrier frequency. The program parameters are: 8.795 µ...
Page 235 8-BIT TIMER A/B S3C8248/C8245/P8245/C8247/C8249/P8249 PROGRAMMING TIP — To generate a one pulse signal through P3.0 This example sets Timer B to the one shot mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 40 µs width pulse. The program parameters are: 40 µ...
Page 236 S3C8248/C8245/P8245/C8247/C8249/P8249 16-BIT TIMER 0/1 16-BIT TIMER 0/1 16-BIT TIMER 0 OVERVIEW The 16-bit timer 0 is an 16-bit general-purpose timer. Timer 0 has the interval timer mode by using the appropriate T0CON setting. Timer 0 has the following functional components: —...
Page 237 16-BIT TIMER 0/1 S3C8248/C8245/P8245/C8247/C8249/P8249 TIMER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to — Enable the timer 0 operating (interval timer) — Select the timer 0 input clock frequency — Clear the timer 0 counter, T0CNT —...
Page 238 S3C8248/C8245/P8245/C8247/C8249/P8249 16-BIT TIMER 0/1 BLOCK DIAGRAM Bits 7, 6, 5 Data Bus Bit 3 TBOF fxx/256 16-bit up-Counter H/L fxx/64 (Read Only) Clear fxx/8 Pending fxx/1 T0INT 16-bit Comparator Bit 0 IRQ2 Match Bit 2 Timer 0 Buffer Reg Bit 1 Counter clear signal (T0CON.3)
Page 239 16-BIT TIMER 0/1 S3C8248/C8245/P8245/C8247/C8249/P8249 Timer 0 Counter High-Byte (T0CNTH) F2H, Set 1, Bank 1, R Reset Value: 00H Timer 0 Counter Low-Byte (T0CNTL) F3H, Set 1, Bank 1, R Reset Value: 00H Figure 12-3. Timer 0 Counter Register (T0CNT) Timer 0 Data High-Byte Register...
Page 240 S3C8248/C8245/P8245/C8247/C8249/P8249 16-BIT TIMER 0/1 16-BIT TIMER 1 OVERVIEW The 16-bit timer 1 is an 16-bit general-purpose timer/counter. Timer 1 has three operating modes, one of which you select using the appropriate T1CON setting: — Interval timer mode (Toggle output at T1OUT pin) —...
Page 241 16-BIT TIMER 0/1 S3C8248/C8245/P8245/C8247/C8249/P8249 FUNCTION DESCRIPTION Timer 1 Interrupts (IRQ3, Vectors E8H and EAH) The timer 1 module can generate two interrupts, the timer 1 overflow interrupt (T1OVF), and the timer 1 match/capture interrupt (T1INT). T1OVF is interrupt level IRQ3, vector EAH. T1INT also belongs to interrupt level IRQ3, but is assigned the separate vector address, E8H.
Page 242 S3C8248/C8245/P8245/C8247/C8249/P8249 16-BIT TIMER 0/1 TIMER 1 CONTROL REGISTER (T1CON) You use the timer 1 control register, T1CON, to — Select the timer 1 operating mode (interval timer, capture mode, or PWM mode) — Select the timer 1 input clock frequency —...
Page 243 16-BIT TIMER 0/1 S3C8248/C8245/P8245/C8247/C8249/P8249 BLOCK DIAGRAM T1CON.0 T1OVF IRQ3 Pending T1CON.7-5 Data Bus T1CON.2 /1024 /256 Clear T1CON.1 16-bit Up-Counter (Read Only) T1CLK T1INT 16-bit Comparator Pending IRQ3 Match T1OUT T1CAP T1PWM Timer 1 Buffer Reg T1CON.4-.3 Counter Clear Signal or Match T1CON.4-.3...
Page 244 S3C8248/C8245/P8245/C8247/C8249/P8249 16-BIT TIMER 0/1 Timer 1 Counter High-Byte Register (T1CNTH) FCH, Set 1, Bank 1, R Reset Value: 00H Timer 1 Counter Low-Byte Register (T1CNTL) FDH, Set 1, Bank 1, R Reset Value: 00H Timer 1 Data High-Byte Register (T1DATAH) FEH, Set 1, Bank 1, R/W...
Page 245 16-BIT TIMER 0/1 S3C8248/C8245/P8245/C8247/C8249/P8249 NOTES 12-10...
Page 246 S3C8248/C8245/P8245/C8247/C8249/P8249 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit1 and bit 6 of the watch timer mode register, WTCON.1and 6, to “1”. After the watch timer starts and elapses a time, the watch timer interrupt is automatically set to “1”, and interrupt...
Page 247 WATCH TIMER S3C8248/C8245/P8245/C8247/C8249/P8249 WATCH TIMER CONTROL REGISTER (WTCON: R/W) WTCON.7 WTCON.6 WTCON.5 WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTCON.0 RESET "0" "0" "0" "0" "0" "0" "0" "0" Table 13-1. Watch Timer Control Register (WTCON): Set 1, Bank 1, FAH, R/W Bit Name...
Page 248 S3C8248/C8245/P8245/C8247/C8249/P8249 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM BUZZER Output WTCON.6 WTCON.5 WTINT WTCON.4 /64 (0.5 kHz) WTCON.3 /32 (1 kHz) /16 (2 kHz) /8 (4 kHz) WTCON.2 Enable/Disable Selector WTCON.1 WTCON.0 Circuit Frequency Clock WTCON.7 Dividing Selector (4096 HZ) 1 Hz Circuit 32.768 kHz...
Page 249 WATCH TIMER S3C8248/C8245/P8245/C8247/C8249/P8249 NOTES 13-4...
Page 250 S3C8248/C8245/P8245/C8247/C8249/P8249 LCD CONTROLLER/DRIVER LCD CONTROLLER/DRIVER OVERVIEW The S3C8248/C8245/C8247/C8249 micro-controller can directly drive an up-to-16-digit (32-segment) LCD panel. The LCD module has the following components: — LCD controller/driver — Display RAM (00H–0FH) for storing display data in page 4 — 32 segment output pins (SEG0–SEG31) —...
Page 251 LCD CONTROLLER/DRIVER S3C8248/C8245/P8245/C8247/C8249/P8249 LCD CIRCUIT DIAGRAM OFH.7 OFH.6 SEG31 OFH.5 SEG30 OFH.4 SEG29 SEG28 SEG27 SEG26 05H.1 05H.0 Segment 04H.7 SEG16 Driver SEG15 04H.6 SEG14 SEG13 SEG12 00H.3 SEG11 00H.2 00H.1 SEG0 00H.0 COM3 COM2 Timing LMOD Controller Control COM1...
Page 252 S3C8248/C8245/P8245/C8247/C8249/P8249 LCD CONTROLLER/DRIVER LCD RAM ADDRESS AREA RAM addresses 00H - 0FH of page 4, or page 2, according to ROM size, are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.
Page 253 LCD CONTROLLER/DRIVER S3C8248/C8245/P8245/C8247/C8249/P8249 LCD CONTROL REGISTER (LCON), D0H Table 14-1. LCD Control Register (LCON) Organization LCON Bit Setting Description LCON.7 P5.4–P5.7 I/O is selected SEG28–SEG31 is selected, P5.4–P5.7 I/O is disabled LCON.6 P5.0–P5.3 I/O is selected SEG24–SEG27 is selected, P5.0–P5.3 I/O is disabled LCON.5...
Page 254 S3C8248/C8245/P8245/C8247/C8249/P8249 LCD CONTROLLER/DRIVER LCD MODE REGISTER (LMOD) The LCD mode control register LMOD is mapped to RAM addresses D1H. LMOD controls these LCD functions: — Duty and bias selection (LMOD.3–LMOD.0) — LCDCK clock frequency selection (LMOD.5–LMOD.4) The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each segment output. This is also referred to as the 'frame frequency.' Since LCDCK is generated by dividing the watch timer clock (fw), the...
Page 255 LCD CONTROLLER/DRIVER S3C8248/C8245/P8245/C8247/C8249/P8249 Table 14-4. LCD Mode Control Register (LMOD) Organization, D1H LMOD.7 Always logic zero. LMOD.6 Always logic zero. LMOD.5 LMOD.4 LCD Clock (LCDCK) Frequency 32.768 kHz watch timer clock (fw)/2 = 64 Hz 32.768 kHz watch timer clock (fw)/2 = 128 Hz 32.768 kHz watch timer clock (fw)/2...
Page 256 S3C8248/C8245/P8245/C8247/C8249/P8249 LCD CONTROLLER/DRIVER LCD DRIVE VOLTAGE The LCD display is turned on only when the voltage difference between the common and segment signals is greater than V . The LCD display is turned off when the difference between the common and segment signal...
Page 257 LCD CONTROLLER/DRIVER S3C8248/C8245/P8245/C8247/C8249/P8249 Select Non-Select 1 Frame LC1, 2 LC 0 LC1, 2 LC 0 LC1, 2 LC 0 COM-SEG LC 0 LC1, 2 Figure 14-5. Select/No-Select Bias Signals in 1/2 Duty, 1/2 Bias Display Mode Select Non-Select 1 Frame...
Page 258 S3C8248/C8245/P8245/C8247/C8249/P8249 LCD CONTROLLER/DRIVER SEG0.0 x C0 1 Frame LC1, 2 COM0 LC1, 2 SEG1.0 x C0 COM1 LC1, 2 SEG0 LC1, 2 SEG2.1 x C1 SEG2.1 x C1 SEG1 SEG3.1 x C1 LC1, 2 COM0 -SEG0 LC1, 2 LC1, 2...
Page 259 LCD CONTROLLER/DRIVER S3C8248/C8245/P8245/C8247/C8249/P8249 SEG2.0 x C0 1 Frame COM0 COM1 SEG2.1 x C1 COM2 SEG0 SEG0.2 x C2 SEG2.1 x C1 SEG1.6 x C2 SEG1 COM0 -SEG0 COM0 -SEG1 COM1 -SEG0 COM1 -SEG1 Figure 14-8. LCD Signals and Wave Forms Example in 1/3 Duty, 1/3 Bias Display Mode...
Page 260 S3C8248/C8245/P8245/C8247/C8249/P8249 LCD CONTROLLER/DRIVER SEG1.4 x C0 1 Frame COM0 COM1 SEG0.1 x C1 COM2 COM3 SEG2.1 x C1 SEG0.3 x C3 SEG1.7 x C3 SEG0 SEG1 COM0 -SEG0 COM0 -SEG1 COM1 -SEG0 COM1 -SEG1 Figure 14-9. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode...
Page 261 LCD CONTROLLER/DRIVER S3C8248/C8245/P8245/C8247/C8249/P8249 LCD VOLTAGE DRIVING METHOD By Voltage Booster For run the voltage booster — Make enable the watch timer for f booster — Set LCON.2 to "0" and LCON.1 to "1" for make enable voltage booster — Recommendable capacitance value is 0.1 uF (CAB, C0, C1, C2)
Page 262 S3C8248/C8245/P8245/C8247/C8249/P8249 A/D CONVERTER 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10-bit digital values. The analog input level must lie between the and AV values.
Page 263 A/D CONVERTER S3C8248/C8245/P8245/C8247/C8249/P8249 CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 8 MHz fxx clock frequency, one clock cycle is 1 us.
Page 264 S3C8248/C8245/P8245/C8247/C8249/P8249 A/D CONVERTER Conversion Data Register (High Byte) ADDATAH F8H, Set 1, Bank 1, Read Only Conversion Data Register (Low Byte) ADDATAL F9H, Set 1, Bank 1, Read Only Figure 15-2. A/D Converter Data Register (ADDATAH/L) INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage.
Page 265 A/D CONVERTER S3C8248/C8245/P8245/C8247/C8249/P8249 BLOCK DIAGRAM ADCON.2-.1 ADCON.4-.6 (Select one input pin of the assigned pins) To ADCON.3 Clock (EOC Flag) Selector ADCON.0 (AD/C Enable) Analog Successive Input Pins Comparator Approximation ADC0-ADC7 Logic & Register (P2.0-P2.7) ADCON.0 Upper 8-bit is loaded to...
Page 266 S3C8248/C8245/P8245/C8247/C8249/P8249 A/D CONVERTER Reference Voltage Input 10 uF Analog ADC0-ADC7 Input Pin S3C8248/C8245 /C8247/C8249 NOTE: The symbol "R" signifies an offset resistor with a value of from 50 to 100Ω. If this resistor is omitted, the absolute accuracy will be maximum of 3 LSBs.
Page 267 A/D CONVERTER S3C8248/C8245/P8245/C8247/C8249/P8249 NOTES 15-6...
Page 268 S3C8248/C8245/P8245/C8247/C8249/P8249 SERIAL I/O INTERFACE SERIAL I/O INTERFACE OVERVIEW Serial I/O module, SIO can interface with various types of external device that require serial data transfer. The components of each SIO function block are: — 8-bit control register (SIOCON) — Clock selector logic —...
Page 269 SERIAL I/O INTERFACE S3C8248/C8245/P8245/C8247/C8249/P8249 SIO CONTROL REGISTER (SIOCON) The control register for serial I/O interface module, SIOCON, is located at F0H in set 1, bank 0. It has the control settings for SIO module. — Clock source selection (internal or external) for shift clock —...
Page 270 S3C8248/C8245/P8245/C8247/C8249/P8249 SERIAL I/O INTERFACE SIO PRE-SCALER REGISTER (SIOPS) The control register for serial I/O interface module, SIOPS, is located at F2H in set 1, bank 0. The value stored in the SIO pre-scale registers, SIOPS, lets you determine the SIO clock rate (baud rate) as...
Page 271 SERIAL I/O INTERFACE S3C8248/C8245/P8245/C8247/C8249/P8249 SERIAL I/O TIMING DIAGRAM Transmit IRQS Complete Set SIOCON.3 Figure 16-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) Transmit IRQS Complete Set SIOCON.3 Figure 16-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
Page 272 S3C8248/C8245/P8245/C8247/C8249/P8249 VOLTAGE BOOSTER VOLTAGE BOOSTER OVERVIEW This voltage booster works for the power control of LCD : generates 3 × V ), 2 × V ), 1 × V This voltage booster allows low voltage operation of LCD display with high quality. This voltage booster circuit provides constant LCD contrast level even though battery power supply was lowered.
Page 273 VOLTAGE BOOSTER S3C8248/C8245/P8245/C8247/C8249/P8249 BLOCK DIAGRAM (2 x V (3 x V Voltage Clock Regulator LCON.1 LCON.0 LCON.2 Figure 17-1. Voltage Booster Block Diagram COM0-3 COM0-3 Drive Drive SEG0-SEG31 SEG0-SEG31 Voltage Voltage Booster Booster Voltage Voltage Regulator Regulator (1.05 V) (1.5 V)
Page 274 VOLTAGE LEVEL DETECTOR OVERVIEW The S3C8248/C8245/C8247/C8249 micro-controller has a built-in VLD (Voltage Level Detector) circuit which allows detection of power voltage drop or external input level through software. Turning the VLD operation on and off can be controlled by software. Because the IC consumes a large amount of current during VLD operation.
Page 275 VOLTAGE LEVEL DETECTOR S3C8248/C8245/P8245/C8247/C8249/P8249 VOLTAGE LEVEL DETECTOR CONTROL REGISTER (VLDCON) The bit 2 of VLDCON controls to run or disable the operation of Voltage level detect. Basically this V is set as 2.2 V by system reset and it can be changed in 4 kinds voltages by selecting Voltage Level Detect Control register (VLDCON).
Page 276 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C8248/C8245/C8247/C8249 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D.C. electrical characteristics — A.C. electrical characteristics —...
Page 277 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-1. Absolute Maximum Ratings ° = 25 Parameter Symbol Conditions Rating Unit Supply voltage – 0.3 to +6.5 – 0.3 to V + 0.3 Input voltage – 0.3 to V + 0.3 Output voltage Output current high One I/O pin active –...
Page 278 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-2. D.C. Electrical Characteristics (Continued) ° ° = -40 C to + 85 C, V = 1.8 V to 5.5 V) Parameter Symbol Conditions Unit = 5 V; I = -1 mA –1.0 Output high voltage –...
Page 279 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-2. D.C. Electrical Characteristics (Concluded) ° ° = -40 C to + 85 C, V = 1.8 V to 5.5 V) Parameter Symbol Conditions Unit = 5 V 10 % ± – Supply current 10 MHz crystal oscillator...
Page 280 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA In case of S3C8248/C8245, the characteristic of V and V is differ with the characteristic of S3C8247/C8249 like as following. Other characteristics are same each other. Table 19-3. D.C Electrical Characteristics of S3C8248/C8245 ° ° = -40...
Page 281 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-4. A.C. Electrical Characteristics ° ° = -40 C to +85 C, V = 1.8 V to 5.5 V) Parameter Symbol Conditions Unit P0.0–P0.7, V = 5 V Interrupt input tINTH, – – high, low width tINTL (P0.0–P0.7)
Page 282 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-5. Input/Output Capacitance ° ° = -40 C to +85 C, V = 0 V ) Parameter Symbol Conditions Unit Input f = 1 MHz; unmeasured pins – – are returned to V capacitance Output capacitance I/O capacitance Table 19-6.
Page 283 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Oscillation Stabilization Time Idle Mode Stop Mode Data Retention Mode DDDR Normal Execution of Operating Mode STOP Instruction Interrupt 0.2 V WAIT NOTE: is the same as 16 x BT clock. WAIT Figure 19-4. Stop Mode (Main) Release Timing Initiated by Interrupts...
Page 284 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-7. A/D Converter Electrical Characteristics = - 40 °C to +85 °C, V = 2.7 V to 5.5 V, V = 0 V) Parameter Symbol Conditions Unit Resolution – – ±3 = 5 V Total accuracy –...
Page 285 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-8. Voltage Booster Electrical Characteristics = 25 °C, V = 2.0 V to 5.5 V, V = 0 V) Parameter Symbol Test Conditions Unit Operating Voltage – = 5 uA (1/3 bias) Regulated Voltage 1.15 Booster Voltage –...
Page 286 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-10. Synchronous SIO Electrical Characteristics ° ° = -40 C to +85 C, V = 1.8 V to 5.5 V, V = 0 V, fxx = 10 MHz oscillator) Parameter Symbol Conditions Unit SCK Cycle time –...
Page 287 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-11. Main Oscillator Frequency (f OSC1 ° ° = -40 C to +85 C, V = 1.8 V to 5.5 V) Oscillator Clock Circuit Test Condition Unit Crystal Crystal oscillation frequency – Ceramic Ceramic oscillation –...
Page 288 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA 1/fosc1, 1/fosc2 , XT - 0.1V 0.1V Figure 19-7. Clock Timing Measurement at X Table 19-13. Sub Oscillator Frequency (f OSC2 ° ° = -40 C + 85 C, V = 1.8 V to 5.5 V) Oscillator...
Page 289 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-14. Sub Oscillator(crystal) Stabilization Time (t ° = 25 Oscillator Test Condition Unit =4.5V to 5.5V Crystal Normal – mode =2.0V to 4.5V – – Crystal Strong =3.0V to 5.5V – – mode =2.0V to 3.0V –...
Page 290 S3C8248/C8245/P8245/C8247/C8249/P8249 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C8248/C8245/C8247/C8249 microcontroller is currently available in 80-pin-QFP/TQFP package. 23.90 ± 0.30 20.00 ± 0.20 + 0.10 0.15 - 0.05 80-QFP-1420C 0.10 MAX 0.35 + 0.10 0.05 MIN 0.80 0.15 MAX (0.80) 2.65 ± 0.10 3.00 MAX...
Page 291 MECHANICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 14.00 BSC 12.00 BSC 0.09-0.20 80-TQFP-1212 0.17-0.27 0.05-0.15 0.08 MAX M 0.50 (1.25) ± 0.05 1.00 1.20 MAX NOTE: Dimensions are in millimeters. Figure 20-2. Package Dimensions (80-TQFP-1212) 20-2...
Page 292 OVERVIEW The S3P8245/P8249 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8248/C8245/C8247/C8249 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P8245/P8249 is fully compatible with the S3C8248/C8245/C8247/C8249, both in function and in pin configuration.
Page 293: P3.1/Taout/Tapwm
S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 SEF26/P5.2 SEG9 SEG27/P5.3 SEG8 SEG28/P5.4 SEG7 SEG29/P5.5 SEG6 SEG30/P5.6 SEG5 SEG31/P5.7 SEG4 P3.0/TBPWM SEG3 P3.1/TAOUT/TAPWM SEG2 P3.2/TACLK SEG1 P3.3/TACAP/SDAT SEG0 S3P8245/P8249 P3.4/SCLK COM3 80-QFP COM2 COM1 COM0 (Top View) VLC2 /TEST VLC1 VLC0 RESET P0.0/INT0 P0.1/INT1 P0.2/INT2 P2.7/ADC7/V...
Page 294 RESET RESET Chip Initialization 12/13 – Logic power supply pin. V should be tied to +5 V during programming. Table 21-2. Comparison of S3P8245/P8249 and S3C8248/C8245/C8247/C8249 Features Characteristic S3P8245/P8249 S3C8248/C8245/C8247/C8249 Program Memory 16K/32K-byte EPROM 16K/32K-byte mask ROM Operating Voltage (V 1.8 V to 5.5 V...
Page 295 S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the V (TEST) pin of the S3P8245/P8249, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 21-3 below.
Page 296 S3C8248/C8245/P8245/C8247/C8249/P8249 S3P8245/P8249 OTP Table 21-4. D.C. Electrical Characteristics (Continued) ° ° = -40 C to +85 C, V = 1.8 V to 5.5 V) Parameter Symbol Conditions Unit – – Input high leakage LIH1 current All input pins except I...
Page 297 S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 Table 21-4. D.C. Electrical Characteristics (Concluded) ° ° = -40 C to + 85 C, V = 1.8 V to 5.5 V) Parameter Symbol Conditions Unit = 5 V 10 % – ± Supply current 10 MHz crystal oscillator...
Page 298 S3P8245/P8249 OTP case of S3P8245, the characteristic of V and V is differ with the characteristic of S3P8249 like as bellow. Other characteristics are same each other. Table 21-5. D.C Electrical Characteristics of S3C8248/C8245 ° ° = -40 C to +85 C, V = 1.8 V to 5.5 V)
Page 299 S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 NOTES 21-8...
Page 300 SMDS2+, and OPENice for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options.
Page 301 DEVELOPMENT TOOLS S3C8248/C8245/P8245/C8247/C8249/P8249 IBM-PC AT or Compatible RS-232C SMDS2+ Target PROM/OTP Writer Unit Application System RAM Break/Display Unit Probe Adapter Trace/Timer Unit TB8249 SAM8 Base Unit Target Board Power Supply Unit Chip Figure 22-1. SMDS Product Configuration (SMDS2+) 22-2...
Page 302 S3C8248/C8245/P8245/C8247/C8249/P8249 DEVELOPMENT TOOLS TB8245/9 TARGET BOARD The TB8245/9 target board is used for the S3C8248/C8245/C8247/C8249 microcontroller. It is supported with the SMDS2+. TB8245/8249 To User_V Device Selection 8245 8249 RESET Idle Stop 7411 J101 J102 144 QFP S3E8240 EVA Chip...
Page 303 DEVELOPMENT TOOLS S3C8248/C8245/P8245/C8247/C8249/P8249 Table 22-1. Power Selection Settings for TB8245/9 "To User_Vcc" Operating Mode Comments Settings The SMDS2/SMDS2+ To User_V supplies V to the target TB8245 Target board (evaluation chip) and TB8249 System the target system. SMDS2/SMDS2+ The SMDS2/SMDS2+ To User_V...
Page 304 S3C8248/C8245/P8245/C8247/C8249/P8249 DEVELOPMENT TOOLS Table 22-3. Device Selection Settings for TB8245/9 "To User_Vcc" Operating Mode Comments Settings Operate with TB8249 Device Selection Target 8245 8249 TB8249 System Operate with TB8245 Device Selection Target 8245 8249 TB8245 System SMDS2+ SELECTION (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows.
Page 305: P3.2/Taclk
DEVELOPMENT TOOLS S3C8248/C8245/P8245/C8247/C8249/P8249 J101 J102 SEG26/P5.2 SEG27/P5.3 P2.5/ADC5 P2.6/ADC6 SEG28/P5.4 SEG29/P5.5 P2.7/ADC7/V VLDREF SEG30/P5.6 SEG31/P5.7 P3.0/TBPWM P3.1/TAOUT/TAPWM P3.2/TACLK P3.3/TACAP/SDAT P3.4/SCLK COM0 COM1 COM2 COM3 TEST SEG0 SEG1 SEG2 SEG3 RESET P0.0/INT0 SEG4 SEG5 P0.1/INT1 P0.2/INT2 SEG6 SEG7 P0.3/INT3 P0.4/INT4 SEG8 SEG9 P0.5/INT5...
Page 306 Replacement of an existing product Other If you are replacing an existing product, please indicate the former product name What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price...
Page 308 _______________________________ _______________________________________ (Person Placing the Risk Order) (SEC Sales Representative) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
Page 310 Office Automation Remocon Other Please describe in detail its application (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
Page 312 Replacement of an existing microcontroller Other If you are replacing an existing microcontroller, please indicate the former microcontroller name What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price...
Page 314 Once you choose a read protection, you cannot read again the programming code from the EPROM. OTP Writing will be executed in our manufacturing site. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors occurred from the writing program.
Page 315 BOOK SPINE TEXT SAMSUNG Logo S3C8248/C8245/P8245/C8247/C8249/P8249 Microcontrollers User's Manual, Rev. 3 March 2002...

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C8245 P8245 C8249 C8247 P8249

Samsung S3C8248 User Manual

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Summary of Contents for Samsung S3C8248

Page 5: Table Of Contents

Page 6: Seg26/P5.2

Page 219: Seg30/P5.6

Page 230: P3.0/Tbpwm

Page 293: P3.1/Taout/Tapwm

Page 305: P3.2/Taclk

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