Samsung S3F84B8 User Manual page 261

S3F84B8_UM_REV 1.00
14.1.1.1.2 Block Diagram of Comparator 0
C0EN (CMP0CON.3)
CMP0_P
CMP0_N
C0PLR (CMP0CON.4)
Fosc
+
CMP0
-
NOTE:
1. Polarity selection bit (CMP 0CON .4) will not affect interrupt generation logic.
2. PWM trigger signal is falling edge active only.
Figure 14-3
INT Enable (CMP0CON.2)
CMP0CON.0
SET
D
Q
Q
CLR
CMP0CON.1
Block Diagram of Comparator 0
14-3
14 COMPARATOR
INT
CTRL
CMPINT.1-.0
PWM
Interrupt