Page 1 S3C9228/P9228 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.10...
Page 2 Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
Page 3 — Chapter 18. S3P9228 OTP — Chapter 19. Development Tools DIRECTIONS: Please note the changes in your copy (copies) of the S3C9228/P9228 User's Manual, Revision 1.00. Or, simply attach the Revision Descriptions of the next page to S3C9228/P9228 User's Manual, Revision 1.00.
Page 4 REVISION DESCRIPTIONS (Rev1.00) 1. BLOCK DIAGRAM: I/O port 6 block should be added to "Figure 1-1. Block Diagram" in the Page 1-3. 2. PIN ASSIGNMENT: The contents of "Disable Stop Instruction" should be changed "00000000B" into "other values" in the Page 4-34, Page 7-7, and Page 8-2.
Page 5 REVISION DESCRIPTIONS (Rev1.10) Chapter Page Location Description The contents for ″48-ELP-0707 Pin Assignments″ is added Figure 1-4 − Programming Tips for switching the CPU clock is updated. Figure 16-1 Partial content is modified. Figure 16-2 Partial content is modified. The contents for ″48-ELP-0707 Package Dimensions″ is added Figure 17-3 The contents for ″S3P9228 48-ELP-0707 Pin Assignments″...
Page 6 Chapter 13 LCD Controller/Driver Two order forms are included at the back of this manual to facilitate customer order for S3C9228/P9228 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.
Page 7: Table Of Contents
Table of Contents Part I — Programming Model Chapter 1 Product Overview SAM88RCRI Product Family......................... 1-1 S3C9228/P9228 Microcontroller ........................1-1 OTP ................................1-1 Features ................................ 1-2 Block Diagram ............................... 1-3 Pin Assignments............................1-4 Pin Descriptions ............................1-7 Pin Circuit Diagrams............................1-9...
Page 8 Enable/Disable Interrupt Instructions (EI, DI) ..................5-1 Interrupt Pending Function Types......................5-2 Interrupt Priority.............................5-2 Interrupt Source Service Sequence......................5-3 Interrupt Service Routines ........................5-3 Generating Interrupt Vector addresses....................5-3 S3C9228/P9228 Interrupt Structure .....................5-4 Chapter 6 SAM88RCRI Instruction Set Overview ................................6-1 Register Addressing..........................6-1 Addressing Modes ..........................6-1 Flags Register (FLAGS)........................6-4...
Page 9 Port 2 ..............................9-9 Port 3 ..............................9-11 Port 4 ..............................9-14 Port 5 ..............................9-15 Port 6 ..............................9-16 Chapter 10 Basic Timer Overview................................ 10-1 Basic Timer Control Register (BTCON) ....................10-2 Basic Timer Function Description......................10-3 S3C9228/P9228_UM_REV1.10 MICROCONTROLLERS...
Page 10 A/D Converter Control Register (ADCON)....................14-2 Internal Reference Voltage Levels......................14-3 Block Diagram ...............................14-3 Chapter 15 Serial I/O Interface Overview ................................15-1 Programming Procedure........................15-1 SIO Control Registers (SIOCON) ......................15-2 SIO Pre-Scaler Register (SIOPS) ......................15-3 SIO Block Diagram ............................15-3 Serial I/O Timing Diagram (SIO) ......................15-4 viii S3C9228/P9228_UM_REV1.10 MICROCONTROLLERS...
Page 11 Chapter 19 Development Tools Overview................................ 19-1 Target Boards ............................19-1 Programming Socket Adapter ......................19-1 TB9228 Target Board ........................... 19-3 Idle LED ..............................19-4 Stop LED .............................. 19-4 Third Parties for Development Tools ....................19-7 OTP/MTP Programmer (WRITER)....................... 19-8 S3C9228/P9228_UM_REV1.10 MICROCONTROLLERS...
Page 12 Pin Circuit Type H-32 ......................1-12 1-11 Pin Circuit Type H-32A......................1-12 1-12 Pin Circuit Type H-32B......................1-13 S3C9228/P9228 Program Memory Address Space ............... 2-2 Internal Register File Organization ..................2-3 16-Bit Register Pairs ....................... 2-4 Stack Operations........................2-5 Register Addressing........................ 3-2 Working Register Addressing ....................
Page 13 System Clock Control Register (CLKCON)................7-4 Oscillator Control Register (OSCCON) ...................7-5 STOP Control Register (STPCON) ..................7-7 S3C9228 I/O Port Data Register Format ................9-2 Port 0 Control Register (P0CON) ....................9-4 Port 0 Interrupt Control Register (P0INT)................9-4 Port 0 Interrupt Pending Bits (INTPND1.3-.0) .................9-5 Port 0 Interrupt Edge Selection Register (P0EDGE)...............9-5...
Page 14 SIO Prescaler Register (SIOPS)..................... 15-3 15-3 SIO Functional Block Diagram....................15-3 15-4 Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)......15-4 15-5 Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)......15-4 S3C9228/P9228_UM_REV1.10 MICROCONTROLLERS xiii...
Page 15 PCB Design Guide for on Board Programming...............18-5 19-1 Emulator Product Configuration ....................19-2 19-2 TB9228 Target Board Configuration ..................19-3 19-3 Connectors (J101, J102) for TB9228 ..................19-5 19-4 S3C9228 Probe Adapter for 42-SDIP Package ..............19-6 19-5 S3C9228 Probe Adapter for 44-QFP Package ...............19-6 S3C9228/P9228_UM_REV1.10 MICROCONTROLLERS...
Page 16 16-10 Sub Oscillation Stabilization Time................... 16-12 18-1 Descriptions of Pins Used to Read/Write the EPROM ............18-3 18-2 Comparison of S3P9228 and S3C9228 Features ..............18-3 18-3 Reference Table for Connection ..................... 18-6 19-1 Components of TB9228 ......................19-4 19-2 Setting of the Jumper in TB9228 ....................
Page 17 Standard Stack Operations Using PUSH and POP ..................2-6 Chapter 5: Interrupt Structure How to clear an interrupt pending bit ......................5-6 Chapter 7: Clock Circuits Switching the CPU clock ..........................7-6 How to Use Stop Instruction.......................... 7-7 S3C9228/P9228_UM_REV1.10 MICROCONTROLLERS xvii...
Page 18 Port 6 Control Register ....................4-32 SIOCON SIO Control Register ....................4-33 STPCON Stop Control Register....................4-34 System Mode Register....................4-35 TACON Timer 1/A Control Register ..................4-36 TBCON Timer B Control Register ................... 4-37 WTCON Watch Timer Control Register..................4-38 S3C9228/P9228_UM_REV1.10 MICROCONTROLLERS...
Page 19 Rotate Right Through Carry..................6-42 Subtract With Carry....................6-43 Set Carry Flag ......................6-44 Shift Right Arithmetic....................6-45 STOP Stop Operation ......................6-46 Subtract ........................6-47 Test Complement Under Mask .................. 6-48 Test Under Mask......................6-49 Logical Exclusive OR ....................6-50 S3C9228/P9228_UM_REV1.10 MICROCONTROLLERS...
Page 20: Chapter 1 Product Overview
S3C9228/P9228 MICROCONTROLLER The S3C9228 can be used for dedicated control functions in a variety of applications, and is especially designed for application with FRS or etc. The S3C9228/P9228 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM88RCRI CPU core.
Page 21: Features
PRODUCT OVERVIEW S3C9228/P9228_UM_REV1.10 FEATURES LCD Controller/Driver • SAM88RCRI CPU core • 16 segments and 8 common terminals • 3, 4, and 8 common selectable Memory • Internal resistor circuit for LCD bias • 8192 × 8 bits program memory (ROM) •...
Page 22: Block Diagram
S3C9228/P9228_UM_REV1.10 PRODUCT OVERVIEW BLOCK DIAGRAM RESET 8-Bit Timer/ Watchdog TAOUT/ 16-Bit CounterA Timer P0.0 Timer/ 8-Bit Timer/ T1CLK/ Counter1 Basic Timer CounterB P0.1 P0.0/TAOUT/INT Port I/O and Interrupt I/O Port 0 P0.1/T1CLK/INT Control Watch Timer BUZ/P0.3 P0.2/INT P0.3/BUZ/INT P0.4 COM0-COM3/P6.3-P6.0 P0.5...
Page 23: Pin Assignments
CO M 6/SEG 17/P5.5 P1.2/AD2/INT CO M 7/SEG 16/P5.4 P1.3/AD3/INT SEG 15/P5.3 S3C9228/ SEG 14/P5.2 S3P9228 SEG 13/P5.1 SEG 12/P5.0 O UT (44-Q FP) SEG 11/P4.7 TEST SEG 10/P4.6 SEG 9/P4.5 SEG 8/P4.4 O UT Figure 1-2. S3C9228 44-QFP Pin Assignments...
Page 24: S3C9228 42-Sdip Pin Assignments
S E G 2 /P 3 .1 /IN T P P 2 .2 /S I S E G 1 /P 2 .0 /S C K S E G 0 /P 2 .1 /S O Figure 1-3. S3C9228 42-SDIP Pin Assignments...
Page 25: S3C9228 48-Elp-0707 Pin Assignments
S3C9228/ SEG 12/P5.0 S3P9228 SEG 13/P5.1 O UT (48-ELP-0707) SEG 14/P5.2 SEG 15/P5.3 (BO TTO M VIEW ) CO M 5/SEG 18/P5.6 P1.3/ADC3/INT CO M 6/SEG 17/P5.5 P1.2/ADC2/INT CO M 7/SEG 16/P5.4 P1.1/ADC1/INT P1.0/ADC0/INT Figure 1-4. S3C9228 48-ELP-0707 Pin Assignments...
Page 26: Pin Descriptions
S3C9228/P9228_UM_REV1.10 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. Pin Descriptions Pin Names Pin Description Circuit Share Type Number Numbers Pins P0.0 1-bit programmable I/O port. Schmitt 39(3/42) TAOUT/INT P0.1 trigger input or push-pull, open-drain 40(4/43) T1CLK/INT P0.2 output and software assignable pull-ups.
Page 27 PRODUCT OVERVIEW S3C9228/P9228_UM_REV1.10 Table 1-1. Pin Descriptions (Continued) Pin Names Pin Description Circuit Share Type Number Numbers Pins – Power input pins for internal power block – – (11, 12/5, 6) – Main oscillator pins for main clock – (13, 14/7, 8) , XT –...
Page 28: Pin Circuit Diagrams
S3C9228/P9228_UM_REV1.10 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS Pull-Up Resistor RESET Noise Filter Figure 1-5. Pin Circuit Type B Data Output Output Disable Figure 1-6. Pin Circuit Type C...
Page 29: Pin Circuit Type E-4
PRODUCT OVERVIEW S3C9228/P9228_UM_REV1.10 Pull-up Resistor Pull-up Open-Drain Enable Data Output Disable External Interrupt Input Figure 1-7. Pin Circuit Type E-4 Pull-up Resistor Pull-up Enable Open-Drain EN Circuit Data Type E Output Disable ADEN ADSELECT Data To ADC Figure 1-8. Pin Circuit Type F-16A...
Page 30: Pin Circuit Type H-23
S3C9228/P9228_UM_REV1.10 PRODUCT OVERVIEW SEG/COM Output Disable Figure 1-9. Pin Circuit Type H-23 1-11...
Page 31: Pin Circuit Type H-32
PRODUCT OVERVIEW S3C9228/P9228_UM_REV1.10 Pull-up Resistor Pull-up Open-Drain EN Enable Data LCD Out EN COM/SEG Circuit Type H-23 Output Disable Figure 1-10. Pin Circuit Type H-32 Pull-up Resistor Pull-up Open-Drain EN Enable Data LCD Out EN COM/SEG Circuit Type H-23 Output Disable Figure 1-11.
Page 32: Pin Circuit Type H-32B
S3C9228/P9228_UM_REV1.10 PRODUCT OVERVIEW Pull-up Resistor Pull-up Open-Drain EN Enable Data Port Enable LCD Out EN (LMOD.5) COM/SEG Circuit Type H-23 Output Disable Figure 1-12. Pin Circuit Type H-32B 1-13...
Page 33 PRODUCT OVERVIEW S3C9228/P9228_UM_REV1.10 NOTES 1-14...
Page 34: Chapter 2 Address Spaces
CPU and the internal register file. The S3C9228 has 8K bytes of mask-programmable program memory on-chip. The S3C9228/P9228 microcontroller has 244 bytes general-purpose registers in its internal register file and the 20 bytes for LCD display memory is implemented in the internal register file too.
Page 35: Program Memory (Rom)
S3C9228/P9228_UM_REV1.10 PROGRAM MEMORY (ROM) Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask-programmable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H–0001H) are an interrupt vector address. The program reset address in the ROM is 0100H.
Page 36: Register Architecture
(00H–BFH). This register file expansion is implemented by page 1 in the S3C9228/P9228. The page 1 (20 × 8 bits) is for LCD display register and can be used as general-purpose registers.
Page 37: Common Working Register Area (C0H-Cfh)
ADDRESS SPACES S3C9228/P9228_UM_REV1.10 COMMON WORKING REGISTER AREA (C0H–CFH) The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file.
Page 38: System Stack
Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C9228/P9228, the SP must be initialized to an 8-bit value in the range 00H–B7H.
Page 39 ADDRESS SPACES S3C9228/P9228_UM_REV1.10 PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SP ← B8H (Normally, the SP is set to 0B8H by the SP,#0B8H ;...
Page 40: Chapter 3 Addressing Modes
S3C9228/P9228_UM_REV1.10 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.
Page 41: Register Addressing Mode (R)
ADDRESSING MODES S3C9228/P9228_UM_REV1.10 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses a 16-byte working register space in the register file and a 4-bit register within that space (see Figure 3-2).
Page 42: Indirect Register Addressing Mode (Ir)
S3C9228/P9228_UM_REV1.10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
Page 43: Indirect Register Addressing To Program Memory
ADDRESSING MODES S3C9228/P9228_UM_REV1.10 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory REGISTER Example PAIR Instruction Points to References OPCODE Rigister Pair Program 16-Bit Memory Address Points to Program Program Memory Memory Sample Instructions: Value used in OPERAND Instruction CALL...
Page 44: Indirect Working Register Addressing To Register File
S3C9228/P9228_UM_REV1.10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory 4-Bit 4 LSBs Working OPERAND Register Point to the OPCODE Address Woking Register (1 of 16) Sample Instruction: Value used in OPERAND Instruction R6, @R2 Figure 3-5. Indirect Working Register Addressing to Register File...
Page 45: Indirect Working Register Addressing To Program Or Data Memory
ADDRESSING MODES S3C9228/P9228_UM_REV1.10 INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File Program Memory 4-Bit Working Register Address Register Next 3 Bits Point Pair OPCODE to Working Example Instruction Register Pair References either 16-Bit (1 of 8) Program Memory or address Data Memory...
Page 46: Indexed Addressing Mode (X)
S3C9228/P9228_UM_REV1.10 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
Page 47: Indexed Addressing To Program Or Data Memory With Short Offset
ADDRESSING MODES S3C9228/P9228_UM_REV1.10 INDEXED ADDRESSING MODE (Continued) Program Memory Register File XS (OFFSET) NEXT 3 Bits 4-Bit Working Register Register Address Point to Working Pair OPCODE Register Pair 16-Bit (1 of 8) address added to offset LSB Selects 16-Bits 8-Bits...
Page 48: Indexed Addressing To Program Or Data Memory With Long Offset
S3C9228/P9228_UM_REV1.10 ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Program Memory Register File (OFFSET) (OFFSET) Register NEXT 3 Bits 4-Bit Working Pair Register Address Point to Working OPCODE 16-Bit Register Pair address (1 of 8) added to offset LSB Selects 16-Bits 8-Bits...
Page 49: Direct Address Mode (Da)
ADDRESSING MODES S3C9228/P9228_UM_REV1.10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
Page 50: Direct Addressing For Call And Jump Instructions
S3C9228/P9228_UM_REV1.10 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16-bit immediate address CALL DISPLAY Where DISPLAY is a 16-bit immediate address Figure 3-11.
Page 51: Relative Address Mode (Ra)
ADDRESSING MODES S3C9228/P9228_UM_REV1.10 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.
Page 52: Chapter 4 Control Registers
CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs.
Page 53 CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 Table 4-1. System and Peripheral Control Registers (Page 0) Register Name Mnemonic Address (Page 0) Decimal Port 0 Control Register P0CON Port 0 Pull-up Resistor Enable Register P0PUR Port 0 Interrupt Control Register P0INT Port 0 Interrupt Edge Selection Register...
Page 54 S3C9228/P9228_UM_REV1.10 CONTROL REGISTERS Table 4-1. System and Peripheral Control Registers (Page 0) Register Name Mnemonic Address (Page 0) Decimal Locations D8H-B9H are not mapped. Timer B Control Register TBCON Timer 1/A Control Register TACON Timer B Data Register TBDATA Timer A Data Register...
Page 55: Register Description Format
CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register address Register bit or bit function (hexadecimal) Full Register name mnemonic FLAGS - System Flags Register Bit Identifier RESET Value Read/Write...
Page 56: Adcon A/D Converter Control Register
— A/D Converter Control Register Bit Identifier RESET Value – – Read/Write – – .7-.6 Not used for the S3C9228/P9228 .5-.4 A/D Input Pin Selection Bits AD0 (P1.0) AD1 (P1.1) AD2 (P1.2) AD3 (P1.3) End of Conversion Bit (Read-only) Conversion not complete Conversion complete .2-.1...
Page 57: Btcon Basic Timer Control Register
CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 BTCON — Basic Timer Control Register Bit Identifier RESET Value Read/Write .7-.4 Watchdog Timer Enable Bits Disable watchdog function Any other value Enable watchdog function .3-.2 Basic Timer Input Clock Selection Bits fxx/4096 fxx/1024 fxx/128 fxx/16 Basic Timer Counter Clear Bit...
Page 58: Clkcon System Clock Control Register
S3C9228/P9228_UM_REV1.10 CONTROL REGISTERS CLKCON — System Clock Control Register Bit Identifier – – – – – RESET Value Read/Write – – – – – Oscillator IRQ Wake-up Function Bit Enable IRQ for main or sub oscillator wake-up in power down mode Disable IRQ for main or sub oscillator wake-up in power down mode .6-.5...
Page 59: Flags System Flags Register
Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1") Overflow Flag (V) Operation result is ≤ +127 or 　 –128 ≤ –128 　 Operation result is +127 or .3-.0 Not used for S3C9228/P9228...
Page 60: Intpnd1 Interrupt Pending Register 1
S3C9228/P9228_UM_REV1.10 CONTROL REGISTERS INTPND1 — Interrupt Pending Register 1 Bit Identifier RESET Value Read/Write P1.3's Interrupt Pending Bit No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) P1.2's Interrupt Pending Bit No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) P1.1's Interrupt Pending Bit...
Page 61: Intpnd2 Interrupt Pending Register 2
RESET Value – – Read/Write .7-.6 Not used for S3C9228/P9228 P3.1 (INTP) Interrupt Pending Bit No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) P3.0 (INTP) Interrupt Pending Bit No interrupt pending (when read), clear pending bit (when write)
Page 62: Lmod Lcd Mode Control Register
— LCD Mode Control Register Bit Identifier – RESET Value – Read/Write Not used for S3C9228/P9228 COM Pins High Impedance Control Bit Normal COMs signal output COM pins are at high impedance Port3 High Impedance Control Bit Normal I/O High impedance input...
Page 63: Lpot Lcd Port Control Register
CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 LPOT — LCD Port Control Register Bit Identifier – RESET Value – Read/Write Not used for S3C9228/P9228 .6-.4 SEG4-SEG19 and COM0-COM3 Selection Bit SEG4-7 SEG8-11 SEG12-15 SEG16-19/ COM0-3 COM7-COM4 P4.0-P4.3 P4.4-P4.7 P5.0-P5.3 P5.4-P5.7 P6.0-P6.3 SEG/COM Port SEG/COM...
Page 64 RESET Value Read/Write – – – – – .7-.4 Not used for S3C9228/P9228 Main Oscillator Control Bit Main oscillator RUN Main oscillator STOP Sub Oscillator Control Bit Sub oscillator RUN Sub oscillator STOP Not used for S3C9228/P9228 System Clock Selection Bit...
Page 65: P0Con Port 0 Control Register
CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 P0CON – Port 0 Control Register Bit Identifier RESET Value Read/Write .7-.6 P0.3/BUZ/INT Configuration Bits Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (BUZ output) .5-.4 P0.2/INT Configuration Bits Schmitt trigger input Push-pull output N-channel open-drain output Not available .3-.2...
Page 66: P0Int Port 0 Interrupt Enable Register
– – – RESET Value Read/Write – – – – .7-.4 Not used for S3C9228/P9228 P0.3's Interrupt Enable Bit Disable interrupt Enable interrupt P0.2's Interrupt Enable Bit Disable interrupt Enable interrupt P0.1's Interrupt Enable Bit Disable interrupt Enable interrupt P0.0's Interrupt Enable Bit...
Page 67: P0Pur Port 0 Pull-Up Resistors Enable Register
– RESET Value Read/Write – – – – .7-.4 Not used for S3C9228/P9228 P0.3's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P0.2's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P0.1's Pull-up Resistor Enable Bit...
Page 68: P0Edge Port 0 Interrupt Edge Selection Register
– RESET Value Read/Write – – – – .7-.4 Not used for S3C9228/P9228 P0.3's Interrupt Edge Setting Bit Falling edge interrupt Rising edge interrupt P0.2's Interrupt State Setting Bit Falling edge interrupt Rising edge interrupt P0.1's Interrupt State Setting Bit...
Page 69: P1Con Port 1 Control Register
CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 P1CON – Port 1 Control Register Bit Identifier RESET Value Read/Write .7-.6 P1.3/AD3/INT Configuration Bits Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (ADC mode) .5-.4 P1.2/AD2/INT Configuration Bits Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (ADC mode) .3-.2...
Page 70: P1Int Port 1 Interrupt Enable Register
– – – RESET Value Read/Write – – – – .7-.4 Not used for S3C9228/P9228 P1.3's Interrupt Enable Bit Disable interrupt Enable interrupt P1.2's Interrupt Enable Bit Disable interrupt Enable interrupt P1.1's Interrupt Enable Bit Disable interrupt Enable interrupt P1.0's Interrupt Enable Bit...
Page 71: P1Pur Port 1 Pull-Up Resistors Enable Register
– RESET Value Read/Write – – – – .7-.4 Not used for S3C9228/P9228 P1.3's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P1.2's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P1.1's Pull-up Resistor Enable Bit...
Page 72: P1Edge Port 1 Interrupt Edge Selection Register
– RESET Value Read/Write – – – – .7-.4 Not used for S3C9228/P9228 P1.3's Interrupt Edge Setting Bit Falling edge interrupt Rising edge interrupt P1.2's Interrupt State Setting Bit Falling edge interrupt Rising edge interrupt P1.1's Interrupt State Setting Bit...
Page 73: P2Con Port 2 Control Register
CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 P2CON – Port 2 Control Register Bit Identifier RESET Value Read/Write .7-.6 P2.3 Configuration Bits Schmitt trigger input Push-pull output N-channel open-drain output Not available .5-.4 P2.2/SI Configuration Bits Schmitt trigger input (SI) Push-pull output N-channel open-drain output Not available .3-.2...
Page 74: P2Pur Port 2 Pull-Up Resistors Enable Register
– RESET Value Read/Write – – – – .7-.4 Not used for S3C9228/P9228 P2.3's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P2.2's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P2.1's Pull-up Resistor Enable Bit...
Page 75: P3Con Port 3 Control Register
– – – – RESET Value Read/Write – – – – .7-.4 Not used for S3C9228/P9228 .3-.2 P3.1/SEG2/INTP Configuration Bits Schmitt trigger input Push-pull output N-channel open-drain output Not available .1-.0 P3.0/SEG3/INTP Configuration Bits Schmitt trigger input Push-pull output N-channel open-drain output...
Page 76 –Port 3 Interrupt Enable Register Bit Identifier – – – – – – RESET Value Read/Write – – – – – – .7-.2 Not used for S3C9228/P9228 P3.1's Interrupt Enable Bit Disable interrupt Enable interrupt P3.0's Interrupt Enable Bit Disable interrupt Enable interrupt 4-25...
Page 77: P3Pur Port 3 Pull-Up Resistors Enable Register
– – – RESET Value Read/Write – – – – – – .7-.2 Not used for S3C9228/P9228 P3.1's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P3.0's Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor 4-26...
Page 78: P3Edge Port 3 Interrupt Edge Selection Register
– – – RESET Value Read/Write – – – – – – .7-.4 Not used for S3C9228/P9228 P3.1's Interrupt State Setting Bit Falling edge interrupt Rising edge interrupt P3.0's Interrupt State Setting Bit Falling edge interrupt Rising edge interrupt 4-27...
Page 79: P4Conh Port 4 Control Register
CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 P4CONH – Port 4 Control Register High Byte Bit Identifier RESET Value Read/Write .7-.6 P4.7/SEG11 Configuration Bits Input mode Push-pull output N-channel open-drain output Input, pull-up mode .5-.4 P4.6/SEG10 Configuration Bits Input mode Push-pull output N-channel open-drain output Input, pull-up mode .3-.2...
Page 80: P4Conl Port 4 Control Register Low Byte
S3C9228/P9228_UM_REV1.10 CONTROL REGISTERS P4CONL –Port 4 Control Register Low Byte Bit Identifier RESET Value Read/Write .7-.6 P4.3/SEG7 Configuration Bits Input mode Push-pull output N-channel open-drain output Input, pull-up mode .5-.4 P4.2/SEG6 Configuration Bits Input mode Push-pull output N-channel open-drain output Input, pull-up mode .3-.2...
Page 81: P5Conh Port 5 Control Register High Byte
CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 P5CONH – Port 5 Control Register High Byte Bit Identifier RESET Value Read/Write .7-.6 P5.7/SEG19/COM4 Configuration Bits Input mode Push-pull output N-channel open-drain output Input, pull-up mode .5-.4 P5.6/SEG18/COM5 Configuration Bits Input mode Push-pull output N-channel open-drain output Input, pull-up mode .3-.2...
Page 82: P5Conl Port 5 Control Register Low Byte
S3C9228/P9228_UM_REV1.10 CONTROL REGISTERS P5CONL – Port 5 Control Register Low Byte Bit Identifier RESET Value Read/Write .7-.6 P5.3/SEG15 Configuration Bits Input mode Push-pull output N-channel open-drain output Input, pull-up mode .5-.4 P5.2/SEG14 Configuration Bits Input mode Push-pull output N-channel open-drain output Input, pull-up mode .3-.2...
Page 83: P6Con Port 6 Control Register
CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 P6CON – Port 6 Control Register High Byte Bit Identifier RESET Value Read/Write .7-.6 P6.3/COM0 Configuration Bits Input mode Push-pull output N-channel open-drain output Input, pull-up mode .5-.4 P6.2/COM1 Configuration Bits Input mode Push-pull output N-channel open-drain output Input, pull-up mode .3-.2...
Page 84: Siocon Sio Control Register
SIO Counter Clear and Shift Start Bit No action Clear 3-bit counter and start shifting SIO Shift Operation Enable Bit Disable shifter and clock counter Enable shifter and clock counter SIO Interrupt Enable Bit Disable SIO interrupt Enable SIO interrupt Not used for S3C9228/P9228 4-33...
Page 85: Stpcon Stop Control Register
CONTROL REGISTERS S3C9228/P9228_UM_REV1.10 STPCON – Stop Control Register Bit Identifier RESET Value Read/Write Stop Control Bits Enable Stop instruction Other values Disable Stop instruction NOTE: Before executing the STOP instruction, the STPCON register must be set to "10100101B". Otherwise the STOP instruction will not execute.
Page 86: Sym System Mode Register
– – RESET Value – – – – Read/Write .7-.4 Not used for S3C9228/P9228 Global Interrupt Enable Bit Global interrupt processing disable (DI instruction) Global interrupt processing enable (EI instruction) .2-.0 Page Selection Bits Page 0 Page 1 Other values...
Page 87: Tacon Timer 1/A Control Register
Timer 1/A Counter Clear Bit No effect Clear the timer 1/A counter (when write) Timer 1/A Counter Enable Bit Disable counting operation Enable counting operation Timer 1/A Interrupt Enable Bit Disable interrupt Enable interrupt Bit 0 Not used for S3C9228/P9228 4-36...
Page 88: Tbcon Timer B Control Register
TBCON — Timer B Control Register Bit Identifier – – RESET Value – – Read/Write Not used for S3C9228/P9228 .6-.4 Timer B Clock Selection Bits fxx/512 fxx/256 fxx/64 fxx/8 fxx (system clock) fxt (sub clock) Timer B Counter Clear Bit...
Page 89: Wtcon Watch Timer Control Register
Set watch timer interrupt to 1s Set watch timer interrupt to 0.5s Set watch timer interrupt to 0.25s Set watch timer interrupt to 3.91ms Watch Timer Enable Bit Disable watch timer; Clear frequency dividing circuits Enable watch timer Not used for S3C9228/P9228 4-38...
Page 90: Chapter 5 Interrupt Structure
S3C9228/P9228_UM_REV1.10 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H–0001H. VECTOR SOURCES 0000H...
Page 91: Interrupt Pending Function Types
INTERRUPT STRUCTURE S3C9228/P9228_UM_REV1.10 INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87RCRI, the order of service is determined by a sequence of source which is executed in interrupt service routine.
Page 92: Interrupt Source Service Sequence
S3C9228/P9228_UM_REV1.10 INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal.
Page 93: S3C9228/P9228 Interrupt Structure
INTERRUPT STRUCTURE S3C9228/P9228_UM_REV1.10 S3C9228/P9228 INTERRUPT STRUCTURE The S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources: — Timer 1/A interrupt — Timer B interrupt — SIO interrupt — Watch Timer interrupt — Four external interrupts for port 0 — Four external interrupts for port 1...
Page 94: S3C9228/P9228 Interrupt Structure
P1.3 External Interrupt 0000H 0001H P1INT.3 INTPND2.0 Timer 1/A Interrupt SYM.3 TACON.1 (EI, DI) INTPND2.1 Timer B Interrupt TBCON.1 INTPND2.2 SIO Interrupt SIOCON.1 Watch Timer Interrupt INTPND2.3 WTCON.1 INTPND2.4 P3.0 Interrupt P3INT.0 INTPND2.5 P3.1 Interrupt P3INT.1 Figure 5-3. S3C9228/P9228 Interrupt Structure...
Page 95: How To Clear An Interrupt Pending Bit
INTERRUPT STRUCTURE S3C9228/P9228_UM_REV1.10 Programming Tip — How to clear an interrupt pending bit As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: INTPND1, #11111011B ; Clear P0.2's interrupt pending bit •...
Page 96: Chapter 6 Sam88Rcri Instruction Set
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET SAM88RCRI INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8-bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file.
Page 97: Instruction Group Summary
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst,src Load dst,src Load program memory dst,src Load external data memory LDCD dst,src Load program memory and decrement LDED dst,src Load external data memory and decrement...
Page 98 S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL Call procedure IRET Interrupt return cc,dst Jump on condition code Jump unconditional cc,dst Jump relative on condition code Return Bit Manipulation Instructions dst,src...
Page 99: Flags Register (Flags)
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 FLAGS REGISTER (FLAGS) The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4 – FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.
Page 100: Instruction Set Notation
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation – Value is unaffected Value is undefined Table 6-3.
Page 101: Instruction Notation Conventions
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Working register pair RRp (p = 0, 2, 4, ..., 14) Register or working register reg or Rn (reg = 0–255, n = 0–15)
Page 102: Opcode Quick Reference
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IRR1 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1...
Page 103 SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – r1,R2 r2,R1 cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ IDLE ↓ ↓ ↓ ↓ ↓ ↓ STOP IRET ↓ ↓ ↓ ↓...
Page 104: Condition Codes
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"...
Page 105: Instruction Descriptions
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...
Page 106: Add With Carry
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Add With Carry dst,src Operation: dst ¨ dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed.
Page 107 SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Add dst,src Operation: dst ¨ dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
Page 108: Logical And
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Logical AND dst,src Operation: dst ¨ dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...
Page 109: Call Procedure
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 CALL — Call Procedure CALL Operation: ¨ SP – 1 ¨ ¨ SP –1 ¨ ¨ The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
Page 110: Complement Carry Flag
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Complement Carry Flag Operation: C ¨ NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
Page 111: Clear
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Clear Operation: dst ¨ "0" The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: →...
Page 112: Complement
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Complement Operation: dst ¨ NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
Page 113: Compare
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Compare dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow"...
Page 114: Decrement
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Decrement Operation: dst ¨ dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise.
Page 115: Disable Interrupts
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Disable Interrupts Operation: SYM (2) ¨ 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
Page 116: Enable Interrupts
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Enable Interrupts Operation: SYM (2) ¨ 1 An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
Page 117: Idle Operation
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected.
Page 118: Increment
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Increment Operation: dst ¨ dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.
Page 119: Interrupt Return
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 IRET — Interrupt Return IRET IRET Operation: FLAGS ¨ @SP SP ¨ SP + 1 PC ¨ @SP SP ¨ SP + 2 SYM(2) ¨ 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter.
Page 120: Jump
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) Operation: If cc is true, PC ¨ dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.
Page 121: Jump Relative
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Jump Relative cc,dst Operation: If cc is true, PC ¨ PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...
Page 122: Load
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Load dst,src Operation: dst ¨ src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc...
Page 123 SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Load (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0,#10H R0 = 10H →...
Page 124: Load Memory
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ¨ src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data memory.
Page 125 SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External...
Page 126: Load Memory And Decrement
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ¨ src rr ¨ rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
Page 127: Load Memory And Increment
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ¨ src rr ¨ rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
Page 128: No Operation
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected.
Page 129: Logical Or
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Logical OR dst,src Operation: dst ¨ dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...
Page 130: Pop From Stack
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Pop From Stack Operation: dst ¨ @SP SP ¨ SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.
Page 131: Push To Stack
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 PUSH — Push To Stack PUSH Operation: SP ¨ SP – 1 @SP ¨ src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.
Page 132: Reset Carry Flag
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Reset Carry Flag Operation: C ¨ 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: Given: C = "1"...
Page 133: Return
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Return Operation: PC ¨ @SP SP ¨ SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
Page 134: Rotate Left
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Rotate Left Operation: C ¨ dst (7) dst (0) ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
Page 135: Rotate Left Through Carry
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Rotate Left Through Carry Operation: dst (0) ¨ C C ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...
Page 136: Rotate Right
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Rotate Right Operation: C ¨ dst (0) dst (7) ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
Page 137: Rotate Right Through Carry
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Rotate Right Through Carry Operation: dst (7) ¨ C C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...
Page 138: Subtract With Carry
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Subtract With Carry dst,src Operation: dst ¨ dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
Page 139: Set Carry Flag
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Set Carry Flag Operation: C ¨ 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode...
Page 140: Shift Right Arithmetic
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Shift Right Arithmetic Operation: dst (7) ¨ dst (7) C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.
Page 141: Stop Operation
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 STOP — Stop Operation STOP Operation: The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input.
Page 142: Subtract
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Subtract dst,src Operation: dst ¨ dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
Page 143: Test Complement Under Mask
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Test Complement Under Mask dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
Page 144: Test Under Mask
S3C9228/P9228_UM_REV1.10 SAM88RCRI INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.
Page 145: Logical Exclusive Or
SAM88RI INSTRUCTION SET S3C9228/P9228_UM_REV1.10 — Logical Exclusive OR dst,src Operation: dst ¨ dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...
Page 146: Chapter 7 Clock Circuit
CLOCK CIRCUITS OVERVIEW The S3C9228 microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency is determined by CLKCON register settings.
Page 147: Main Oscillator Circuits
CLOCK CIRCUITS S3C9228/P9228_UM_REV1.10 MAIN OSCILLATOR CIRCUITS SUB OSCILLATOR CIRCUITS 32.768 kHz Figure 7-4. Crystal/Ceramic Oscillator Figure 7-1. Crystal/Ceramic Oscillator Figure 7-5. External Oscillator Figure 7-2. External Oscillator Figure 7-3. RC Oscillator...
Page 148: Clock Status During Power-Down Modes
S3C9228/P9228_UM_REV1.10 CLOCK CIRCUITS CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (When the fx is selected as system clock).
Page 149: System Clock Control Register (Clkcon)
00 = fxx/16 1 = Disable IRQ for main oscillator 01 = fxx/8 wake-up function in power down 10 = f mode 11 = fxx Not used for S3C9228 (must keep always "0") Figure 7-7. System Clock Control Register (CLKCON)
Page 150: Oscillator Control Register (Osccon)
Oscillator Control Register (OSCCON) D3H, R/W System clock selection bit: 0 = Main oscillator select 1 = Sub oscillator select Not used for S3C9228 Not used for S3C9228 Sub oscillator control bit: 0 = Sub oscillator RUN 1 = Sub oscillator STOP...
Page 151: Switching The Cpu Clock
CLOCK CIRCUITS S3C9228/P9228_UM_REV1.10 SWITCHING THE CPU CLOCK Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies.
Page 152: Stop Control Register (Stpcon)
S3C9228/P9228_UM_REV1.10 CLOCK CIRCUITS STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions: — Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values".
Page 153 CLOCK CIRCUITS S3C9228/P9228_UM_REV1.10 NOTES...
Page 154: Chapter 8 Reset And Power-Down
CPU clock. This procedure brings S3C9228/P9228 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance.
Page 155: Power-Down Modes
ROM location 0100H. Using an External Interrupt to Release Stop Mode External interrupts can be used to release stop mode. For the S3C9228 microcontroller, we recommend using the INT interrupt, P0, P1, and P3.
Page 156: Idle Mode
S3C9228/P9228_UM_REV1.10 RESET and POWER-DOWN Using an Internal Interrupt to Release Stop Mode An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. If system clock is sub clock, you can't use any interrupts to release stop mode.
Page 157: Hardware Reset Values
RESET and POWER-DOWN S3C9228/P9228_UM_REV1.10 HARDWARE RESET VALUES Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode. The following notation is used in these table to represent specific RESET values: —...
Page 158 S3C9228/P9228_UM_REV1.10 RESET and POWER-DOWN Table 8-1. Register Values after RESET (Continued) Register Name Mnemonic Address Bit Values after RESET System Mode Register – – – – STOP Control Register STPCON SIO Control Register SIOCON – SIO Data Register SIODATA SIO Prescaler Register...
Page 159 RESET and POWER-DOWN S3C9228/P9228_UM_REV1.10 NOTES...
Page 160: Chapter 9 I/O Ports
The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. All ports of the S3C9228/P9228 except P0.4 and P0.5 can be configured to input or output mode. All LCD signal pins are shared with normal I/O ports.
Page 161: Port Data Registers
PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. Data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1.
Page 162: Port 0
S3C9228/P9228_UM_REV1.10 I/O PORTS PORT 0 Port 0 is a 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E4H in page 0. P0.0-P0.3 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions.
Page 163: Port 0 Control Register (P0Con)
I/O PORTS S3C9228/P9228_UM_REV1.10 Port 0 Control Register (P0CON) EBH, Page 0, R/W P0.3/BUZ P0.2 P0.1/T1CLK P0.0/TAOUT (INT) (INT) (INT) (INT) P0CON bit-pair pin configuration settings: Schmitt trigger input mode (T1CLK) Push-pull output mode N-channel open-drain output mode Alternative function (TAOUT, BUZ) Figure 9-2.
Page 164: Port 0 Interrupt Pending Bits (Intpnd1.3-.0)
S3C9228/P9228_UM_REV1.10 I/O PORTS Port 0 Interrupt Pending Bits (INTPND1.3-.0) D6H, Page 0, R/W P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT) INTPND1 bit configuration settings: No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) Figure 9-4.
Page 165: Port 1
I/O PORTS S3C9228/P9228_UM_REV1.10 PORT 1 Port 1 is a 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E5H in page 0. P1.0-P1.3 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions.
Page 166: Port 1 Interrupt Control Register (P1Int)
S3C9228/P9228_UM_REV1.10 I/O PORTS Port 1 Interrupt Control Register (P1INT) F1H, Page 0, R/W P1.3 P1.2 P1.1 P1.0 Not used (INT) (INT) (INT) (INT) P1INT bit configuration settings: Disable interrupt Enable interrupt Figure 9-8. Port 1 Interrupt Control Register (P1INT) Port 1 Interrupt Pending Bits (INTPND1.7-.4) D6H, Page 0, R/W P1.3...
Page 167: Port 1 Interrupt Edge Selection Register (P1Edge)
I/O PORTS S3C9228/P9228_UM_REV1.10 Port 1 Interrupt Edge Selection Register (P1EDGE) F2H, Page 0, R/W P1.3 P1.2 P1.1 P1.0 Not used (INT) (INT) (INT) (INT) P1EDGE bit configuration settings: Falling edge detection Rising edge detection Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE)
Page 168: Port 2
S3C9228/P9228_UM_REV1.10 I/O PORTS PORT 2 Port 2 is a 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E6H in page 0. P2.0-P2.3 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions.
Page 169: Port 2 Pull-Up Control Register (P2Pur)
I/O PORTS S3C9228/P9228_UM_REV1.10 Port 2 Pull-up Control Register (P2PUR) F4H, Page 0, R/W Not used P2.3 P2.2 P2.1 P2.0 P2PUR bit configuration settings: Disable pull-up resistor Enable pull-up resistor Figure 9-13. Port 2 Pull-up Control Register (P2PUR) 9-10...
Page 170: Port 3
S3C9228/P9228_UM_REV1.10 I/O PORTS PORT 3 Port 3 is a 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E7H in page 0. P3.0-P3.1 can serve as inputs (with or without pull-up, and high impedance input), as outputs (push-pull or open-drain) or you can be configured the following functions.
Page 171: Port 3 Interrupt Control Register (P3Int)
I/O PORTS S3C9228/P9228_UM_REV1.10 Port 3 Interrupt Control Register (P3INT) F7H, Page 0, R/W P3.1 P3.0 Not used (INTP) (INTP) P3INT bit configuration settings: Disable interrupt Enable interrupt Figure 9-15. Port 3 Interrupt Control Register (P3INT) Port 3 Interrupt Pending Bits (INTPND2.5-.4)
Page 172: Port 3 Interrupt Edge Selection Register (P3Edge)
S3C9228/P9228_UM_REV1.10 I/O PORTS Port 3 Interrupt Edge Selection Register (P3EDGE) F8H, Page 0, R/W P3.1 P3.0 Not used (INTP) (INTP) P3EDGE bit configuration settings: Falling edge detection Rising edge detection Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE) Port 3 Pull-up Control Register (P3PUR)
Page 173: Port 4
I/O PORTS S3C9228/P9228_UM_REV1.10 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E8H in page 0. P4.0-P4.7 can serve as inputs or as push-pull, open-drain outputs.
Page 174: Port 5
S3C9228/P9228_UM_REV1.10 I/O PORTS PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E9H in page 0. P5.0-P5.7 can serve as inputs or as push-pull, open-drain outputs.
Page 175: Port 6
I/O PORTS S3C9228/P9228_UM_REV1.10 PORT 6 Port 6 is a 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location EAH in page 0. P6.0-P6.3 can serve as inputs or as push-pull, open-drain outputs.
Page 176: Chapter 10 Basic Timer
S3C9228/P9228_UM_REV1.10 BASIC TIMER BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
Page 177: Basic Timer Control Register (Btcon)
BASIC TIMER S3C9228/P9228_UM_REV1.10 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH, and is read/write addressable using Register addressing mode.
Page 178: Basic Timer Function Description
S3C9228/P9228_UM_REV1.10 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to “00H”, automatically enabling the watchdog timer function.
Page 179: Basic Timer Block Diagram
BASIC TIMER S3C9228/P9228_UM_REV1.10 RESET or STOP Bit 1 Bits 3, 2 Basic Timer Control Register (Write '1010xxxxB' to Disable) Data Bus /4096 Clear /1024 8-Bit Up Counter /128 (BTCNT, Read-Only) RESET (note) Start the CPU Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
Page 180: Timer 1
S3C9228/P9228_UM_REV1.10 TIMER 1 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers.
Page 181: Timer 1 Control Register (Tacon)
TIMER 1 S3C9228/P9228_UM_REV1.10 Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to — Enable the timer 1 operating (interval timer) — Select the timer 1 input clock frequency — Clear the timer 1 counter, TACNT and TBCNT —...
Page 182: Timer 1 Block Diagram (One 16-Bit Mode)
S3C9228/P9228_UM_REV1.10 TIMER 1 BTCON.0 TACON.6-.4 1/512 TACON.3 Data Bus 1/256 TACON.2 or XT 1/64 Clear TBCNT TACNT TACON.1 Match 16-Bit Comparator INTPND2.0 T1INT T1CLK TAOUT TBDATA TADATA Buffer Buffer Match Signal Counter clear signal TBDATA TADATA Data Bus NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1) Figure 11-2.
Page 183: Two 8-Bit Timers Mode (Timer A And B)
TIMER 1 S3C9228/P9228_UM_REV1.10 TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively.
Page 184: Timer A Control Register (Tacon)
S3C9228/P9228_UM_REV1.10 TIMER 1 TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt.
Page 185: Timer B Control Register (Tbcon)
TIMER 1 S3C9228/P9228_UM_REV1.10 Timer B Control Register (TBCON) BAH, R/W Not used Not used Timer B match interrupt enable bit: Timer B clock selection bits: 0 = Disable match interrupt 000 = fxx/512 1 = Enable match interrupt 001 = fxx/256...
Page 186: Function Description
S3C9228/P9228_UM_REV1.10 TIMER 1 FUNCTION DESCRIPTION Interval Timer Function (Timer A and Timer B) The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). The timer A match interrupt pending condition (INTPND2.0) and the timer B match interrupt pending condition (INTPND2.1) must be cleared by software in the application's interrupt service by means of writing a "0"...
Page 187: Timer A Block Diagram (Two 8-Bit Timers Mode)
TIMER 1 S3C9228/P9228_UM_REV1.10 BTCON.0 TACON.6-.4 1/512 TACON.3 1/256 Data Bus TACON.2 or XT 1/64 Clear TACNT (8-Bit Up-Counter) TACON.1 Match 8-Bit Comparator INTPND2.0 TAINT T1CLK/ TAOUT P0.1 TADATA Buffer Match Signal Counter Clear Signal TADATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A) Figure 11-5.
Page 188: Timer B Block Diagram (Two 8-Bit Timers Mode)
S3C9228/P9228_UM_REV1.10 TIMER 1 BTCON.0 TBCON.6-.4 1/512 TBCON.3 Data Bus 1/256 TBCON.2 or XT Clear 1/64 TBCNT (8-Bit Up-Counter) TBCON.1 Match 8-Bit Comparator INTPND2.1 TBINT TBDATA Buffer Match Signal Counter Clear Signal TBDATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B) Figure 11-6.
Page 189 TIMER 1 S3C9228/P9228_UM_REV1.10 NOTES 11-10...
Page 190: Chapter 12 Watch Timer
S3C9228/P9228_UM_REV1.10 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt, then set the WTCON.6 to “1”.
Page 191: Watch Timer Control Register (Wtcon)
WATCH TIMER S3C9228/P9228_UM_REV1.10 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode.
Page 192: Watch Timer Circuit Diagram
S3C9228/P9228_UM_REV1.10 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM WTCON.7 WTCON.6 WT INT Enable BUZ (P0.3) WTCON.6 WTCON.5 WTCON.4 WTINT /64 (0.5 kHz) WTCON.3 /32 (1 kHz) /16 (2 kHz) /8 (4 kHz) WTCON.2 Enable/Disable Selector WTCON.1 INTPND2.3 Circuit WTCON.0 Frequency Clock...
Page 193 WATCH TIMER S3C9228/P9228_UM_REV1.10 NOTES 12-4...
Page 194: Chapter 13 Lcd Controller/Driver
S3C9228/P9228_UM_REV1.10 LCD CONTROLLER/DRIVER LCD CONTROLLER/DRIVER OVERVIEW The S3C9228/P9228 microcontroller can directly drive an up-to-128-dot (16segments x 8 commons) LCD panel. Its LCD block has the following components: — LCD controller/driver — Display RAM for storing display data — 16 segment output pins (SEG0–SEG15) —...
Page 195: Lcd Circuit Diagram
LCD CONTROLLER/DRIVER S3C9228/P9228_UM_REV1.10 LCD CIRCUIT DIAGRAM Port Latch SEG15/P5.3 Control Display (Page1) Selector SEG0/P2.1 LPOT COM7/SEG16/P5.4 Control Timing Controller selector COM4/SEG19/P5.7 COM3/P6.0 Port Control Latch COM0/P6.3 LMOD Voltage Control P3.1/INTP/SEG2 Port 3 Port Control Latch P3.0/INTP/SEG3 Figure 13-2. LCD Circuit Diagram...
Page 196: Lcd Ram Address Area
S3C9228/P9228_UM_REV1.10 LCD CONTROLLER/DRIVER LCD RAM ADDRESS AREA RAM addresses of page 1 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.
Page 197: Lcd Mode Control Register (Lmod)
LCD CONTROLLER/DRIVER S3C9228/P9228_UM_REV1.10 LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in page 0, at address FEH, and is read/write addressable using register addressing mode. It has the following control functions. — LCD duty and bias selection — LCD clock selection —...
Page 198: Lcd Port Control Register
S3C9228/P9228_UM_REV1.10 LCD CONTROLLER/DRIVER LCD PORT CONTROL REGISTER The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET, a LPOT values are cleared to "0". LCD Port Control Register D8H, R/W SEG0/P2.1 selection bit:...
Page 199: Lcd Voltage Dividing Resistors
LCD CONTROLLER/DRIVER S3C9228/P9228_UM_REV1.10 LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias 1/4 Bias 1/3 Bias S3C9228/P9228 S3C9228/P9228 S3C9228/P9228 LMOD.4 LMOD.4 LMOD.4 Figure 13-6. Internal Voltage Dividing Resistor Connection COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
Page 200: Lcd Signal Waveforms (1/8 Duty, 1/4 Bias)
S3C9228/P9228_UM_REV1.10 LCD CONTROLLER/DRIVER COM0 0 1 2 3 0 1 2 3 COM1 COM2 COM3 1 Frame COM4 COM5 COM6 COM7 COM0 COM1 COM2 SEG0 + 1/4V SEG0-COM0 - 1/4V Figure 13-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) 13-7...
Page 201: Lcd Signal Waveforms (1/4 Duty, 1/3 Bias)
LCD CONTROLLER/DRIVER S3C9228/P9228_UM_REV1.10 SEG0 SEG1 COM0 1 Frame COM1 COM2 COM0 COM3 COM1 COM2 COM3 SEG0 SEG1 + 1/3 V COM0-SEG0 - 1/3 V Figure 13-8. LCD Signal Waveforms (1/4 Duty, 1/3 Bias) 13-8...
Page 202: Lcd Signal Waveforms (1/3 Duty, 1/3 Bias)
S3C9228/P9228_UM_REV1.10 LCD CONTROLLER/DRIVER SEG1 SEG0 SEG2 COM0 1 Frame COM1 COM0 COM2 COM1 COM2 SEG0 SEG1 + 1/3 V COM0-SEG0 - 1/3 V Figure 13-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias) 13-9...
Page 203 LCD CONTROLLER/DRIVER S3C9228/P9228_UM_REV1.10 NOTES 13-10...
Page 204: Overview
S3C9228/P9228_UM_REV1.10 A/D CONVERTER 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10-bit digital values. The analog input level must lie between the and AV values.
Page 205: Conversion Timing
A/D CONVERTER S3C9228/P9228_UM_REV1.10 CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us.
Page 206: Internal Reference Voltage Levels
S3C9228/P9228_UM_REV1.10 A/D CONVERTER Conversion Data Register ADDATAH/ADDATAL D1H/D2H, Page 0, Read Only LSB (ADDATAH) LSB (ADDATAL) Figure 14-2. A/D Converter Data Register (ADDATAH/ADDATAL) INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input...
Page 207: Recommended A/D Converter Circuit For Highest Absolute Accuracy
A/D CONVERTER S3C9228/P9228_UM_REV1.10 Analog AD0-AD3 Input Pin S3C9228 ≤ ADC input ≤ V Figure 14-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy 14-4...
Page 208: Serial I/O Interface
S3C9228/P9228_UM_REV1.10 SERIAL I/O INTERFACE SERIAL I/O INTERFACE OVERVIEW Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are: — 8-bit control register (SIOCON) — Clock selector logic —...
Page 209: Sio Control Registers (Siocon)
SERIAL I/O INTERFACE S3C9228/P9228_UM_REV1.10 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in page 0. It has the control setting for SIO module. — Clock source selection (internal or external) for shift clock —...
Page 210: Sio Pre-Scaler Register (Siops)
S3C9228/P9228_UM_REV1.10 SERIAL I/O INTERFACE SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0. The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock.
Page 211: Serial I/O Timing Diagram (Sio)
SERIAL I/O INTERFACE S3C9228/P9228_UM_REV1.10 SERIAL I/O TIMING DIAGRAM (SIO) Transmit SIO INT Complete Set SIOCON.3 Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) Transmit SIO INT Complete Set SIOCON.3 Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
Page 212: Chapter 16 Electrical Data
S3C9228/P9228_UM_REV1.10 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in Stop mode —...
Page 213: Absolute Maximum Ratings
ELECTRICAL DATA S3C9228/P9228_UM_REV1.10 Table 16-1. Absolute Maximum Ratings ° = 25 Parameter Symbol Conditions Rating Unit Supply voltage – – 0.3 to + 6.5 Input voltage Ports 0–6 – 0.3 to V + 0.3 – 0.3 to V + 0.3 Output voltage –...
Page 214 S3C9228/P9228_UM_REV1.10 ELECTRICAL DATA Table 16-2. D.C. Electrical Characteristics (Continued) ° ° = – 25 C to + 85 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit μA = 0 V; Input Low – – –3 LIL1...
Page 215 ELECTRICAL DATA S3C9228/P9228_UM_REV1.10 Table 16-2. D.C. Electrical Characteristics (Concluded) ° ° = – 25 C to + 85 C, V = 2.0 V to 5.5 V) Unit Parameter Symbol Conditions Run mode: 8.0 MHz – 12.0 Supply current = 5 V ± 10% Crystal oscillator 4.19 MHz...
Page 216: Stop Mode Release Timing When Initiated By An External Interrupts
S3C9228/P9228_UM_REV1.10 ELECTRICAL DATA Table 16-3. Data Retention Supply Voltage in Stop Mode ° ° = – 25 C to + 85 Parameter Symbol Conditions Unit Data retention supply – – DDDR voltage ° Data retention supply – – µA Stop mode, T...
Page 217: Stop Mode Release Timing When Initiated By Nreset
ELECTRICAL DATA S3C9228/P9228_UM_REV1.10 nRESET Oscillation Occurs Stabilization Time Stop Mode Normal Data Retention Mode Operating Mode DDDR Execution of STOP Instrction nRESET 0.8 V 0.2 V WAIT NOTE: is the same as 4096 x 16 x 1/fxx. WAIT Figure 16-2. Stop Mode Release Timing when initiated by nRESET Table 16-4.
Page 218: A.c. Electrical Characteristics
S3C9228/P9228_UM_REV1.10 ELECTRICAL DATA Table 16-5. A.C. Electrical Characteristics ° ° = – 25 C to + 85 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit SCK cycle time External SCK source 1,000 – – Internal SCK source...
Page 219: Input Timing For External Interrupts
ELECTRICAL DATA S3C9228/P9228_UM_REV1.10 Table 16-6. A/D Converter Electrical Characteristics ° ° = – 25 C to + 85 C, V = 2.7 V to 5.5 V, V = 0 V) Parameter Symbol Conditions Unit Resolution – – ±3 Total accuracy VDD = 5.12 V...
Page 220: Input Timing For Reset
S3C9228/P9228_UM_REV1.10 ELECTRICAL DATA RESET 0.2 V Figure 16-4. Input Timing for RESET 0.8V 0.2V 0.8V 0.2V Output Data Figure 16-5. Serial Data Transfer Timing 16-9...
Page 221: Main Oscillation Characteristics
ELECTRICAL DATA S3C9228/P9228_UM_REV1.10 Table 16-7. Main Oscillation Characteristics ° ° = – 25 C to + 85 Oscillator Clock Configuration Parameter Test Condition Units Crystal Main oscillation 2.7 V – 5.5 V – frequency 2.0 V – 5.5 V –...
Page 222: Main Oscillation Stabilization Time
S3C9228/P9228_UM_REV1.10 ELECTRICAL DATA Table 16-9. Main Oscillation Stabilization Time ° ° = – 25 C to + 85 C, V = 2.0 V to 5.5 V) Oscillator Test Condition Unit Crystal fx > 1 MHz – – Ceramic Oscillation stabilization occurs when VDD is –...
Page 223: Sub Oscillation Stabilization Time
ELECTRICAL DATA S3C9228/P9228_UM_REV1.10 Table 16-10. Sub Oscillation Stabilization Time ° ° = – 25 C to + 85 C, V = 2.0 V to 5.5 V) Oscillator Test Condition Unit Crystal – – – μs input high and low width (t External clock –...
Page 224: Operating Voltage Range
S3C9228/P9228_UM_REV1.10 ELECTRICAL DATA Instruction Clock fx (Main/Sub oscillation frequency) 2 MHz 8 MHz 1.0 MHz 4 MHz 400 kHz 6.25 kHz (main)/8.2 kHz(sub) 400 kHz (main)/32.8 kHz(sub) Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 16-8.
Page 225 ELECTRICAL DATA S3C9228/P9228_UM_REV1.10 NOTES 16-14...
Page 226: Chapter 17 Mechanical Data
S3C9228/P9228_UM_REV1.10 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP, 44-pin QFP and 48-pin ELP package. 0-15 42-SDIP-600 39.50 MAX 39.10 ± 0.2 0.50± 0.1 1.78 (1.77) 1.00 ± 0.1 NOTE: Dimensions are in millimeters.
Page 227: Qfp-1010B Package Dimensions
MECHANICAL DATA S3C9228/P9228_UM_REV1.10 ± 0.3 13.20 ± 0.2 10.00 + 0.10 0.15 - 0.05 44-QFP-1010B 0.10 MAX + 0.10 0.35 - 0.05 0.05 MIN 0.80 (1.00) ± 0.10 2.05 2.30 MAX NOTE: Dimensions are in millimeters. Figure 17-2. 44-QFP-1010B Package Dimensions...
Page 228: Elp-0707 Package Dimensions
S3C9228/P9228_UM_REV1.10 MECHANICAL DATA ± 0.10 7.00 ± 0.05 6.75 48-ELP-0707 (3.74) + 0.10 0.20 - 0.02 0.10 MAX (0.75) 0.50 BSC 0.08 ± 0.05 0.45 0.65 REF 0~0.05 NOTE: Dimensions are in millimeters. Figure 17-3. 48-ELP-0707 Package Dimensions 17-3...
Page 229 MECHANICAL DATA S3C9228/P9228_UM_REV1.10 NOTES 17-4...
Page 230: Overview
It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P9228 is fully compatible with the S3C9228, both in function and in pin configuration. Because of its simple programming requirements, the S3P9228 is ideal for use as an evaluation chip for the S3C9228.
Page 231: S3P9228 42-Sdip Pin Assignments
S3P9228 OTP S3C9228/P9228_UM_REV1.10 C O M 2 /P 6 .1 C O M 1 /P 6 .2 C O M 3 /P 6 .0 C O M 0 /P 6 .3 C O M 4 /S E G 1 9 /P 5 .7 P 0 .0 /T A O U T /IN T...
Page 232 S3C9228/P9228_UM_REV1.10 S3P9228 OTP SEG 8/P4.4 SEG 9/P4.5 O UT SEG 10/P4.6 SEG 11/P4.7 TEST S3P9228 SEG 12/P5.0 (48-ELP-0707) SEG 13/P5.1 O UT SEG 14/P5.2 (BO TTO M VIEW ) SEG 15/P5.3 CO M 5/SEG 18/P5.6 SCLK/P1.3/ADC3/INT CO M 6/SEG 17/P5.5 SDAT/P1.2/ADC2/INT...
Page 233 5 (11/5) – 6 (12/6) + 5 V during programming. NOTE: Parentheses indicate pin number for 42-SDIP and 48-ELP package. Table 18-2. Comparison of S3P9228 and S3C9228 Features Characteristic S3P9228 S3C9228 Program Memory 8K-byte EPROM 8K-byte mask ROM Operating Voltage (V 2.0 V to 5.5 V...
Page 234: On Board Writing
S3C9228/P9228_UM_REV1.10 S3P9228 OTP ON BOARD WRITING The S3P9228 needs only 6 signal lines including V and V pins for writing internal flash memory with serial protocol. Therefore the on-board writing is possible if the writing signal lines are considered when the PCB of application board is designed.
Page 235: Reference Table For Connection
S3P9228 OTP S3C9228/P9228_UM_REV1.10 Reference Table for Connection Table 18-3. Reference Table for Connection Pin Name I/O mode Resistor Required value in Applications (need) is 10 Kohm ~ 50 Kohm. (TEST) Input is 0.01uF ~ 0.02uF. is 2 Kohm ~ 5 Kohm.
Page 236: Chapter 19 Development Tools
TB9228 is a specific target board for the development of application systems using S3C9228/P9228. PROGRAMMING SOCKET ADAPTER When you program S3C9228/P9228 one time programmable memory by using an emulator or OTP writer, you need a standard programming socket adapter for S3C9228/P9228. 19-1...
Page 237: Emulator Product Configuration
DEVELOPMENT TOOLS S3C9228/P9228_UM_REV1.10 IBM-PC AT or Compatible Emulator [SK-1200 (RS-232, USB) RS-232C/USB or OPENice i-500 (RS-232) ] Target OTP/MTP Writer Block Application System RAM Break/Display Block Probe Adapter Trace/Timer Block TB9228 Target SAM8 Base Block Board EVAChip Power Supply Block Figure 19-1.
Page 238: Tb9228 Target Board
S3C9228/P9228_UM_REV1.10 DEVELOPMENT TOOLS TB9228 TARGET BOARD The TB9228 target board can be used for development of the S3C9228 microcontroller. The TB9228 target board is operated as target CPU with Emulator (SK-1200, OPENice-i500)). TB9228 REV.0 In-Circuit Emulator To User_V '2002.03.30 (SK-1200, OPENice-i500)
Page 239: Idle Led
DEVELOPMENT TOOLS S3C9228/P9228_UM_REV1.10 Table 19-1. Components of TB9228 Symbols Usage Description 100-pin connector Connection between emulator and TB9228 target board. J101 50-pin connector Connection between target board and user application system (42-SDIP). J102 50-pin connector Connection between target board and user application...
Page 240: Connectors (J101, J102) For Tb9228
S3C9228/P9228_UM_REV1.10 DEVELOPMENT TOOLS J101 J102 42-SDIP 44-QFP P6.2 P6.1 P1.0 P0.5 P6.3 P6.0 P1.1 P0.4 P0.0 P5.7 P1.2 P0.3 P0.1 P5.6 P1.3 P0.2 P0.2 P5.5 USER_VCC P0.1 P0.3 P5.4 P0.0 P1.0 P5.3 P6.3 P1.1 P5.2 P6.2 P1.2 P5.1 P6.1 P1.3 P5.0...
Page 241: S3C9228 Probe Adapter For 42-Sdip Package
J101 J101 Target Cable for Connector Part Name: AP42SD Order Code: SM6538 21 22 21 22 Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package Target Board Target System J102 J102 Target Cable for 50-pin Connector Part Name: AP50D-A Order Code: SM6305...
Page 242: Third Parties For Development Tools
DEVELOPMENT TOOLS THIRD PARTIES FOR DEVELOPMENT TOOLS SAMSUNG provide a complete line of development tools for SAMSUNG's microcontroller. With long experience in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In-circuit emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with an OTP/MTP programmer.
Page 243: Otp/Mtp Programmer (Writer)
• URL: programmer http://www.seminix.com (Read, Program, Verify, Blank, Protection..) • Fast programming speed (4Kbyte/sec) • Support all of SAMSUNG OTP/MTP/FLASH MCU devices • Low-cost • NOR Flash memory (SST, Samsung…) • NAND Flash memory (SLC) • New devices will be supported just by adding device files or upgrading the software.
Page 244 • PC-based menu-drive software for simple operation • Very fast program and verify time ( OTP:2Kbytes per second, MTP:10Kbytes per second) • Support Samsung standard Hex or Intel Hex format • Driver software run under various O/S (Windows 95/98/2000/XP) • Full function regarding OTP/MTP programmer (Read, Program, Verify, Blank, Protection..)
Page 245 DEVELOPMENT TOOLS S3C9228/P9228_UM_REV1.10 NOTES 19-10...

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S3p9228

Samsung S3C9228 User Manual

Table of Contents

List of Instruction Descriptions

Chapter 1 Product Overview

Chapter 2 Address Spaces

Chapter 3 Addressing Modes

Chapter 4 Control Registers

Chapter 5 Interrupt Structure

Chapter 6 SAM88RCRI Instruction Set

Chapter 7 Clock Circuit

Chapter 8 RESET and Power-Down

Chapter 9 I/O Ports

Chapter 10 Basic Timer

Chapter 11 TIMER 1

Chapter 12 Watch Timer

Chapter 13 LCD Controller/Driver

Chapter 16 Electrical Data

Chapter 17 Mechanical Data

Chapter 19 Development Tools

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Summary of Contents for Samsung S3C9228