Register Architecture - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

2.3 REGISTER ARCHITECTURE

In the S3F84B8 microcontroller implementation, the upper 64 byte area of register files is expanded into two 64
byte areas called set 1 and set 2. The upper 32 byte area of set 1 is further expanded into two 32 byte register
banks called bank 0 and bank 1, while the lower 32 byte area specifies a single 32 byte common area.
In case of S3F84B8, the total number of addressable 8-bit registers is 336. Of these 336 registers, 15 bytes are
meant for the CPU and system control registers, 49 bytes are meant for peripheral control and data registers, 16
bytes are meant for shared working registers. 272 registers are meant for general-purpose use, page 0 (For more
information about page 0, refer to
Registers in Set 1 can only be addressed using register addressing modes.
The extension of register space into separately addressable areas (sets, banks, and pages) is supported by
various addressing mode restrictions, select bank instructions (SB0 and SB1), and register page pointer (PP).
shows the specific register types and area (in bytes) they occupy in the register file.
Table 2-1
System and peripheral registers
General-purpose registers (including the 16-bit common working register area)
Total Addressable Bytes
Figure 2-3).
Table 2-1 S3F84B8 Register Type Summary
Register Type
2-4
2 ADDRESS SPACES
Number of Bytes
64
272
336