Adcon — A/D Converter Control Register: Fah, Bank0 - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
4.1.1 ADCON — A/D CONVERTER CONTROL REGISTER: FAH, BANK0
Bit Identifier
RESET Value
Read/Write
.7–.5
.4
.3
.2–.1
.0
NOTE: Maximum ADC clock input = 4MHz.
.7 .6
0 0
R/W R/W
A/D Converter Input Pin Selection Bits
0 0 0 ADC0 (P2.0)
0 0 1 ADC1 (P2.1)
0 1 0 ADC2 (P2.2)
0 1 1 ADC3 (P2.3)
1 0 0 ADC4 (P2.4)
1 0 1 ADC5 (P2.5)
1 1 0 ADC6 (P2.6)
1 1 1 ADC7 (P2.7)
AD Conversion Completion Interrupt Enable Bit
0 Disables ADC Interrupt.
1 Enables ADC Interrupt.
A/DC Interrupt Pending Bit (EOC)
0 No interrupt is pending, conversion is in progress
(clears pending bit when write).
1 Interrupt is pending, conversion has completed (no effect when write).
Clock Source Selection Bit (Note)
0 0 f /8 (f
OSC OSC
0 1 f /4 (f
OSC OSC
1 0
f /2 (f
OSC OSC
1 1 f /1 (f
OSC OSC
Conversion Start Bit
0 No effect
1 Starts A/D conversion.
.5 .4
0 0
R/W R/W R/W
 10MHz)
 10MHz)
 8MHz)
 4MHz)
4-5
4 CONTROL REGISTERS
.3 .2 .1
0 0 0
R/W R/W
.0
0
R/W