Samsung S3C9454B User Manual
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Samsung S3C9454B User Manual

Samsung S3C9454B User Manual

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S3C9454B/F9454B
8-BIT CMOS
MICROCONTROLLER
USER'S MANUAL
Revision 1

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Summary of Contents for Samsung S3C9454B

  • Page 1 S3C9454B/F9454B 8-BIT CMOS MICROCONTROLLER USER'S MANUAL Revision 1...
  • Page 2 Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
  • Page 3 Chapter 16 Development Tools Two order forms are included at the back of this manual to facilitate customer order S3C9454B/F9454B microcon- trollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.

  • Page 4: Table Of Contents

    Table of Contents Part I — Programming Model Chapter 1 Product Overview SAM88RCRI Product Family......................... 1-1 S3C9454B/F9454B Microcontroller....................... 1-1 MTP................................1-1 Features ................................ 1-2 Block Diagram............................... 1-3 Pin Assignments ............................1-4 Pin Descriptions ............................1-6 Pin Circuits ..............................1-7 Chapter 2 Address Spaces Overview ...............................
  • Page 5 Enable/Disable Interrupt Instructions (EI, DI) ..................5-2 Interrupt Pending Function Types......................5-2 Interrupt Priority ............................5-2 Interrupt Source Service Sequence......................5-3 Interrupt Service Routines ........................5-3 Generating Interrupt Vector Addresses ....................5-3 S3C9454B/F9454B Interrupt Structure....................5-4 Chapter 6 SAM88RCRI Instruction Set Overview................................6-1 Register Addressing ..........................6-1 Addressing Modes ..........................6-1 Flags Register (FLAGS) ........................6-4...
  • Page 6 Module Overview ............................10-1 Basic Timer (BT) ............................10-2 Basic Timer Control Register (BTCON) ....................10-2 Basic Timer Function Description ......................10-3 Timer 0 ................................10-7 Timer 0 Control Registers (T0CON)..................... 10-7 Timer 0 Function Description ....................... 10-8 S3C9454B/F9454B MICROCONTROLLER...
  • Page 7 Overview................................13-1 Chapter 14 Mechanical Data Overview................................14-1 Chapter 15 S3F9454B MTP Overview ..................................15-1 Operating Mode Characteristics ........................15-3 Chapter 16 Development Tools Overview................................16-1 SHINE..............................16-1 SAMA Assembler..........................16-1 SASM86..............................16-1 HEX2ROM ............................16-1 Target Boards ............................16-2 Mtps ..............................16-2 TB9454B Target Board.........................16-3 viii S3C9454B/F9454B MICROCONTROLLER...
  • Page 8 Direct Addressing for Call and Jump Instructions ................3-11 3-12 Relative Addressing..........................3-12 3-13 Immediate Addressing ........................3-12 Register Description Format......................4-4 S3F9-Series Interrupt Type ..................... 5-1 Interrupt Function Diagram...................... 5-2 S3C9454B/F9454B Interrupt Structure ................... 5-4 System Flags Register (FLAGS) ..................... 6-4 S3C9454B/F9454B MICROCONTROLLER...
  • Page 9 Main Oscillator Circuit (Crystal/Ceramic Oscillator)..............7-1 System Clock Control Register (CLKCON) ................7-2 System Clock Circuit Diagram ....................7-3 Reset Block Diagram .......................8-2 Timing for S3C9454B/F9454B After RESET ................8-2 Port Data Register Format.......................9-2 Port 0 Circuit Diagram ......................9-3 Port 0 Control Register (P0CONH, High Byte) ................9-4 Port 0 Control Register (P0CONL, Low Byte).................9-5...
  • Page 10 16-1 SMDS2+ or SK-1000 Product Configuration ................16-2 16-2 TB9454B Target Board Configuration ..................16-3 16-3 DIP Switch for Smart Option ....................16-5 16-4 20-Pin Connector for TB9454B ....................16-6 16-5 S3C9454B/F9454B Probe Adapter for 20-DIP Package............16-6 S3C9454B/F9454B MICROCONTROLLER...
  • Page 11 LVR Circuit Characteristics ..................... 13-9 15-1 Descriptions of Pins Used to Read/Write the Flash ROM............15-3 15-2 Comparison of S3F9454B and S3C9454B Features .............. 15-3 15-3 Operating Mode Selection Criteria ..................15-3 16-1 Power Selection Settings for TB9454B ................... 16-4 16-2 The SMDS2+ Tool Selection Setting..................
  • Page 12 Addressing the Common Working Register Area..................2-7 Standard Stack Operations Using PUSH and POP....................2-9 Chapter 8: RESET and Power-Down Sample S3C9454B/F9454B Initialization Routine ....................8-6 Chapter 10: Basic Timer and Timer 0 Configuring the Basic Timer............................10-6 Configuring Timer 0 (Interval Mode) ........................10-11...
  • Page 13 Port 2 Control Register (High Byte) ................4-13 P2CONL Port 2 Control Register (Low Byte)................4-14 PWMCON PWM Control Register ....................4-15 STOPCON STOP Mode Control Register..................4-16 System Mode Register ....................4-16 T0CON TIMER 0 Control Register ..................4-17 S3C9454B/F9454B MICROCONTROLLER xvii...
  • Page 14 Interrupt Return ......................6-24 Jump........................... 6-25 Jump Relative......................6-26 Load ........................... 6-27 Load ........................... 6-28 LDC/LDE Load Memory ......................6-29 LDC/LDE Load Memory ......................6-30 LDCD/LDED Load Memory and Decrement..................6-31 LDCI/LDEI Load Memory and Increment ..................6-32 S3C9454B/F9454B MICROCONTROLLER...
  • Page 15 Rotate Left ........................6-39 Rotate Left Through Carry..................6-40 Rotate Right........................6-41 Rotate Right Through Carry..................6-42 Subtract With Carry ....................6-43 Set Carry Flag......................6-44 Shift Right Arithmetic ....................6-45 STOP Stop Operation......................6-46 Subtract ........................6-47 Test Complement Under Mask...................6-48 Test Under Mask ......................6-49 Logical Exclusive OR....................6-50 S3C9454B/F9454B MICROCONTROLLER...

  • Page 16: Chapter 1 Product Overview

    The S3C9454B/F9454B has 4K bytes of on-chip program ROM and 208 bytes of RAM. The S3C9454B/F9454B is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring simple timer/counter, PWM.

  • Page 17: Features

    PRODUCT OVERVIEW S3C9454B/F9454B FEATURES Timer/Counters • • SAM88RCRI CPU core One 8-bit basic timer for watchdog function • • The SAM88RCRI core is low-end version of the One 8-bit timer/counter with time interval modes current SAM87 core. A/D Converter Memory •...

  • Page 18: Block Diagram

    S3C9454B/F9454B PRODUCT OVERVIEW BLOCK DIAGRAM P0.0/ADC0/INT0 P0.1/ADC1/INT1 Port 0 P0.2/ADC2 Port I/O and Interrupt Control P0.7/ADC7 Basic Timer P1.0 Timer 0 Port 1 P1.1 88RCRI P1.2 SAMRI CPU ADC0-ADC8 P2.0/T0 P2.1 Port 2 208 Byte 4 KB ROM P0.6/PWM Register File P2.6...

  • Page 19: Pin Assignments

    PRODUCT OVERVIEW S3C9454B/F9454B PIN ASSIGNMENTS /P1.0 P0.0/ADC0/INT0 /P1.1 P0.1/ADC1/INT1 nRESET/P1.2 P0.2/ADC2 S3C9454B/F9454B P2.0/T0 P0.3/ADC3 P2.1 P0.4/ADC4 (20-DIP-300A/ 20-SOP-375/ P2.2 P0.5/ADC5 20-SSOP-225) P2.3 P0.6/ADC6/PWM P2.4 P0.7/ADC7 P2.5 P2.6/ADC8/CLO Figure 1-2. Pin Assignment Diagram (20-Pin DIP/SOP/SSOP Package)
  • Page 20 S3C9454B/F9454B PRODUCT OVERVIEW /P1.0 P0.0/ADC0/INT0 S3C9454B/F9454B /P1.1 P0.1/ADC1/INT1 nRESET/P1.2 P0.2/ADC2 (16-DIP-300A/ P2.0/T0 P0.3/ADC3 16-SOP-BD300-SG/ 16-SSOP-BD44) P2.1 P0.4/ADC4 P2.2 P0.5/ADC5 P2.3 P0.6/ADC6/PWM Figure 1-3. Pin Assignment Diagram (16-Pin DIP/SOP/SSOP Package)

  • Page 21: Pin Descriptions

    PRODUCT OVERVIEW S3C9454B/F9454B PIN DESCRIPTIONS Table 1-1. S3C9454B/F9454B Pin Descriptions Input/ Pin Description Share Name Output Type Pins P0.0–P0.7 Bit-programmable I/O port for Schmitt trigger input or ADC0–ADC7 push-pull output. Pull-up resistors are assignable by INT0/INT1 software. Port0 pins can also be used as A/D converter input, PWM output or external interrupt input.

  • Page 22: Pin Circuits

    S3C9454B/F9454B PRODUCT OVERVIEW PIN CIRCUITS P-channel N-channel Figure 1-5. Pin Circuit Type A Figure 1-6. Pin Circuit Type B Pull-up Enable Data Data Circuit Output Type C Output DIsable Disable Digital Input Figure 1-7. Pin Circuit Type C Figure 1-8. Pin Circuit Type D...
  • Page 23 PRODUCT OVERVIEW S3C9454B/F9454B Open-drain Enable Pull-up enable P2CONH P2CONL P-CH Alternative Data Output P2.x N-CH Output Disable (Input Mode) Digital Input Analog Input Enable Figure 1-9. Pin Circuit Type E Pull-up enable P0CONH P-CH Alternative Output Data P0.x N-CH Output Disable...
  • Page 24 S3C9454B/F9454B PRODUCT OVERVIEW Open-drain Enable Pull-up enable P1.x Output Disable (Input Mode) Pull-down enable Digital Input Figure 1-11. Pin Circuit Type E-2...
  • Page 25 PRODUCT OVERVIEW S3C9454B/F9454B NOTES 1-10...

  • Page 26: Chapter 2 Address Spaces

    A 12-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file. The S3C9454B/F9454B have 4-Kbytes of mask-programmable on-chip program memory: which is configured as the Internal ROM mode, all of the 4-Kbyte internal program memory is used.

  • Page 27: Program Memory (Rom)

    PROGRAM MEMORY (ROM) Normal Operating Mode The S3C9454B/F9454B have 4-Kbytes (locations 0H–0FFFH) of internal mask-programmable program memory. The first 2-bytes of the ROM (0000H–0001H) are interrupt vector address. Unused locations (0002H–00FFH except 3CH, 3DH, 3EH, 3FH) can be used as normal program memory.
  • Page 28 Smart option is the ROM option for starting condition of the chip. The ROM addresses used by smart option are from 003CH to 003FH. The S3C9454B/F9454B only use 003EH, 003FH. Not used ROM address 003CH, 003DH should be initialized to be initialized to 00H. The default value of ROM is FFH (LVR enable, internal RC oscillator).
  • Page 29 PROGRAMMING TIP — Smart Option Setting << Interrupt Vector Address >> 0000H Vector 00H, INT_9454 ; S3C9454B/F9454B has only one interrupt vector << Smart Option Setting >> 003CH ; 003CH, must be initialized to 0. ; 003DH, must be initialized to 0.

  • Page 30: Register Architecture

    ADDRESS SPACES REGISTER ARCHITECTURE The upper 64-bytes of the S3C9454B/F9454B's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 192-bytes of internal register file(00H–BFH) is called the general purpose register space. 234 registers in this space can be accessed; 208 are available for general- purpose use.
  • Page 31 ADDRESS SPACES S3C9454B/F9454B Peripheral Control Registers 64 Bytes of Common Area System Control Registers Working Registers General Purpose Register File 192 Bytes and Stack Area Figure 2-3. Internal Register File Organization...

  • Page 32: Common Working Register Area (C0H-Cfh)

    Typically, these working registers serve as temporary buffers for data operations between different pages. However, because the S3C9454B/F9454B uses only page 0, you can use the common area for any internal data operation.

  • Page 33: System Stack

    Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C9454B/F9454B, the SP must be initialized to an 8- bit value in the range 00H–0C0H.
  • Page 34 S3C9454B/F9454B ADDRESS SPACES PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SP ← C0H (Normally, the SP is set to C0H by the SP,#0C0H ;...
  • Page 35 ADDRESS SPACES S3C9454B/F9454B NOTES 2-10...

  • Page 36: Chapter 3 Addressing Modes

    S3C9454B/F9454B ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.

  • Page 37: Register Addressing Mode (R)

    ADDRESSING MODES S3C9454B/F9454B REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses an 16-byte working register space in the register file and an 4-bit register within that space (see Figure 3-2).

  • Page 38: Indirect Register Addressing Mode (Ir)

    S3C9454B/F9454B ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
  • Page 39 ADDRESSING MODES S3C9454B/F9454B INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory REGISTER Example PAIR Instruction Point to References OPCODE register pair Program 16-bit Memory address points to program Program Memory memory Value used in OPERAND instruction Sample Instructions: CALL...
  • Page 40 S3C9454B/F9454B ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory 4-Bit 4 LSBs Working OPERAND Register Point to the OPCODE Address working register (1 of 16) Sample Instruction: Value used in OPERAND instruction R6, @R2 Figure 3-5. Indirect Working Register Addressing to Register File...
  • Page 41 ADDRESSING MODES S3C9454B/F9454B INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File Program Memory 4-Bit Working Register Address Register Next 3 Bits Point Pair OPCODE to working Example instruction register pair references either 16-Bit (1 of 8) program memory or address data memory...

  • Page 42: Indexed Addressing Mode (X)

    S3C9454B/F9454B ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
  • Page 43 ADDRESSING MODES S3C9454B/F9454B INDEXED ADDRESSING MODE (Continued) Program Memory Register File XS (OFFSET) NEXT 3 Bits 4-Bit Working Register Register Address Point to working Pair OPCODE register pair 16-Bit (1 of 8) address added to offset LSB Selects 16-Bit 8-Bit...
  • Page 44 S3C9454B/F9454B ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Program Memory Register File XLH (OFFSET) XLL (OFFSET) Register NEXT 3 Bits 4-Bit Working Pair Register Address Point to working OPCODE 16-Bit register pair address (1 of 8) added to offset LSB Selects...

  • Page 45: Direct Address Mode (Da)

    ADDRESSING MODES S3C9454B/F9454B DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
  • Page 46 S3C9454B/F9454B ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16-bit immediate address CALL DISPLAY Where DISPLAY is a 16-bit immediate address Figure 3-11.

  • Page 47: Relative Address Mode (Ra)

    ADDRESSING MODES S3C9454B/F9454B RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.

  • Page 48: Chapter 4 Control Registers

    CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9454B/F9454B control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs.
  • Page 49 CONTROL REGISTERS S3C9454B/F9454B Table 4-1. System and Peripheral Control Registers Register name Mnemonic Address & Location RESET value (Bit) Address Timer 0 counter register T0CNT Timer 0 data register T0DATA Timer 0 control register T0CON – – – Location D3H is not mapped...
  • Page 50 S3C9454B/F9454B CONTROL REGISTERS Table 4-1. System and Peripheral Control Registers (Continued) Register Name Mnemonic Address Bit Values After RESET Port 0 data register Port 1 data register – – – – – Port 2 data register – Locations E3H–E5H are not mapped...
  • Page 51 CONTROL REGISTERS S3C9454B/F9454B Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register address Register bit or related bits (hexadecimal) Register name FLAGS - System Flags Register Bit Identifier RESET Value Read/Write Carry Flag (C)
  • Page 52 S3C9454B/F9454B CONTROL REGISTERS ADCON — A/D Converter Control Register Bit Identifier RESET Value Read/Write .7–.4 A/D Converter Input Pin Selection Bits ADC0 (P0.0) ADC1 (P0.1) ADC2 (P0.2) ADC3 (P0.3) ADC4 (P0.4) ADC5 (P0.5) ADC6 (P0.6) ADC7 (P0.7) ADC8 (P2.6) Connected with GND internally...
  • Page 53 CONTROL REGISTERS S3C9454B/F9454B BTCON — Basic Timer Control Register Bit Identifier RESET Value Read/Write .7–.4 Watchdog Timer Function Enable Bit Disable watchdog timer function Others Enable watchdog timer function .3–.2 Basic Timer Input Clock Selection Code /4096 /1024 /128 Invalid setting...
  • Page 54 Oscillator IRQ Wake-up Function Enable Bit Enable IRQ for main system oscillator wake-up function Disable IRQ for main system oscillator wake-up function .6–.5 Not used for S3C9454B/F9454B .4–.3 Divided by Selection Bits for CPU Clock frequency Divide by 16 (f...
  • Page 55 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1") Overflow Flag (V) Operation result is ≤ + 127 or ≥ – 128 Operation result is > + 127 or < – 128 .3–.0 Not used for S3C9454B/F9454B...
  • Page 56 S3C9454B/F9454B CONTROL REGISTERS P0CONH — Port 0 Control Register (High Byte) Bit Identifier RESET Value Read/Write .7–.6 Port 0, P0.7/INT7 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output A/D converter input (ADC7); Schmitt trigger input off .5–.4...
  • Page 57 CONTROL REGISTERS S3C9454B/F9454B P0CONL — Port 0 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7–.6 Port 0, P0.3/INT3 Configuration Bits Schmitt trigger input Schmitt trigger input; pull-up enable Push-pull output A/D converter input (ADC3); Schmitt trigger input off .5–.4...
  • Page 58 Read/Write – – – – .7–.4 Not used for the S3C9454B/F9454B Port 0.1/ADC1/INT1 Interrupt Enable Bit INT1 falling edge interrupt disable INT1 falling edge interrupt enable Port 0.1/ADC1/INT1 Interrupt Pending Bit No interrupt pending (when read) Pending bit clear (when write)
  • Page 59 Configure P1.1 as a n-channel open-drain output Port 1.0 N-channel open-drain Enable Bit Configure P1.0 as a push-pull output Configure P1.0 as a n-channel open-drain output .5–.4 Not used for S3C9454B/F9454B .3–.2 Port 1, P1.1 Interrupt Pending Bits Schmitt trigger input; Schmitt trigger input; pull-up enable Output Schmitt trigger input;...
  • Page 60 P2CONH — Port 2 Control Register (High Byte) Bit Identifier RESET Value – Read/Write – Not used for the S3C9454B/F9454B .6–.4 Port 2, P2.6/ADC8/CLO Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input ADC input Push-pull output Open-drain output; pull-up enable Open-drain output Alternative function;...
  • Page 61 CONTROL REGISTERS S3C9454B/F9454B P2CONL — Port 2 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7–.6 Part 2, P2.3 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output .5–.4 Port 2, P2.2 Configuration Bits Schmitt trigger input;...
  • Page 62 RESET Value – Read/Write – .7–.6 PWM Input Clock Selection Bits Not used for S3C9454B/F9454B PWMDATA Reload Interval Selection Bit Reload from 8-bit up counter overflow Reload from 6-bit up counter overflow PWM Counter Clear Bit No effect Clear the PWM counter (when write)
  • Page 63 .7–.3 Not used for S3C9454B/F9454B Global Interrupt Enable Bit Disable all interrupts Enable all interrupt .2–.0 Page Select Bits Page 0 Page 1 (Not used for S3C9454B/F9454B) Page 2 (Not used for S3C9454B/F9454B) Page 3 (Not used for S3C9454B/F9454B) 4-16...
  • Page 64 – .7–.6 Timer 0 Input Clock Selection Bits /4096 /256 .5–.4 Not used for the S3C9454B/F9454B Timer 0 Counter Clear Bit No effect Clear the timer 0 counter (when write) Not used for the S3C9454B/F9454B Timer 0 Interrupt Enable Bit...
  • Page 65 CONTROL REGISTERS S3C9454B/F9454B NOTES 4-18...

  • Page 66: Chapter 5 Interrupt Structure

    S3C9454B/F9454B INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through an interrupt vector which is assigned in ROM address 0000H. VECTOR SOURCES 0000H...

  • Page 67: Enable/Disable Interrupt Instructions (Ei, Di)

    INTERRUPT STRUCTURE S3C9454B/F9454B ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The system mode register, SYM (DFH), is used to enable and disable interrupt processing. SYM.3 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.3. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing.

  • Page 68: Interrupt Source Service Sequence

    S3C9454B/F9454B INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal.

  • Page 69: S3C9454B/F9454B Interrupt Structure

    INTERRUPT STRUCTURE S3C9454B/F9454B S3C9454B/F9454B INTERRUPT STRUCTURE The S3C9454B/F9454B microcontroller has four peripheral interrupt sources: — PWM overflow — Timer 0 match — P0.0 external interrupt — P0.1 external interrupt Vector Pending Bits Enable/Disable Source Timer 0 Match T0CON.0 T0CON.1 PWM Overflow PWMCON.0...

  • Page 70: Chapter 6 Sam88Rcri Instruction Set

    S3C9454B/F9454B SAM88RCRI INSTRUCTION SET SAM88RCRI INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8-bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file.
  • Page 71 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst,src Load dst,src Load program memory dst,src Load external data memory LDCD dst,src Load program memory and decrement LDED dst,src Load external data memory and decrement...
  • Page 72 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL Call procedure IRET Interrupt return cc,dst Jump on condition code Jump unconditional cc,dst Jump relative on condition code Return Bit Manipulation Instructions dst,src...

  • Page 73: Flags Register (Flags)

    SAM88RCRI INSTRUCTION SET S3C9454B/F9454B FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4–FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.

  • Page 74: Instruction Set Notation

    S3C9454B/F9454B SAM88RCRI INSTRUCTION SET INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation – Value is unaffected Value is undefined Table 6-3.
  • Page 75 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Working register pair RRp (p = 0, 2, 4, ..., 14) Register or working register reg or Rn (reg = 0–255, n = 0–15)
  • Page 76 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IRR1 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1...
  • Page 77 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – r1,R2 r2,R1 cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ IDLE ↓ ↓ ↓ ↓ ↓ ↓ STOP IRET ↓ ↓ ↓ ↓...

  • Page 78: Condition Codes

    S3C9454B/F9454B SAM88RCRI INSTRUCTION SET CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal.

  • Page 79: Instruction Descriptions

    SAM88RCRI INSTRUCTION SET S3C9454B/F9454B INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM87RI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...
  • Page 80 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Add with Carry dst,src dst ← dst + src + c Operation: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected.
  • Page 81 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
  • Page 82 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...
  • Page 83 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B CALL — Call Procedure CALL ← Operation: SP – 1 ← ← SP –1 ← ← The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
  • Page 84 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
  • Page 85 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Clear dst ← "0" Operation: The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: →...
  • Page 86 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise.
  • Page 87 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Compare dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: Set if a "borrow"...
  • Page 88 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is – 128 (80H) and result value is + 127 (7FH);...
  • Page 89 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Disable Interrupts SYM (2) ← 0 Operation: Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
  • Page 90 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Enable Interrupts SYM (2) ← 1 Operation: An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
  • Page 91 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected.
  • Page 92 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. Flags: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise.
  • Page 93 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B IRET — Interrupt Return IRET IRET FLAGS ← @SP Operation: SP ← SP + 1 PC ← @SP SP ← SP + 2 SYM(2) ← 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter.
  • Page 94 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.
  • Page 95 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...
  • Page 96 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc...
  • Page 97 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Load (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0,#10H R0 = 10H →...
  • Page 98 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes "Irr"...
  • Page 99 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
  • Page 100 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
  • Page 101 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
  • Page 102 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected.
  • Page 103 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...
  • Page 104 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.
  • Page 105 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B PUSH — Push To Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.
  • Page 106 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: Given: C = "1"...
  • Page 107 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
  • Page 108 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
  • Page 109 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Rotate Left Through Carry dst (0) ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...
  • Page 110 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
  • Page 111 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Rotate Right Through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...
  • Page 112 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Subtract With Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
  • Page 113 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. Flags: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex)
  • Page 114 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.
  • Page 115 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input.
  • Page 116 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
  • Page 117 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Test Complement Under Mask dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
  • Page 118 S3C9454B/F9454B SAM88RCRI INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.
  • Page 119 SAM88RCRI INSTRUCTION SET S3C9454B/F9454B — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...

  • Page 120: Chapter 7 Clock Circuit

    = 5 V) depending on smart option. An external RC oscillation source provides a typical 4 MHz clock for S3C9454B/F9454B. An internal capacitor supports the RC oscillator circuit. An external crystal or ceramic oscillation source provides a maximum 10 MHz clock.

  • Page 121: Clock Status During Power-Down Modes

    Stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with RC-delay noise filter (for S3C9454B/F9454B, INT0–INT1). — In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The current CPU status is preserved, including stack pointer, program counter, and flags.
  • Page 122 P2CONH.6-.4 INT Pin NOTE: An external interrupt (with RC-delay noise filter) can be used to release stop mode and "wake-up" the main oscillator. In the S3C9454B/F9454B, the INT0-INT1 external interrupts are of this type. Figure 7-4. System Clock Circuit Diagram...
  • Page 123 CLOCK CIRCUIT S3C9454B/F9454B NOTES...

  • Page 124: Chapter 8 Reset And Power-Down

    Schmitt trigger circuit where it is then synchronized with the CPU clock. This brings the S3C9454B/F9454B into a known operating status. To ensure correct start-up, the user should take care that nRESET signal is not released before the V level is sufficient to allow MCU operation at the chosen frequency.
  • Page 125 Internal nRESET LVR nRESET Watchdog nRESET Figure 8-1. Reset Block Diagram Oscillation Stabilization Wait Time (6.55 ms/at 10 MHz) nRESET Input Operation Mode Idle Mode Normal Mode or Power-Down Mode RESET Operation Figure 8-2. Timing for S3C9454B/F9454B After RESET...

  • Page 126: Power-Down Modes

    Using an External Interrupt to Release Stop Mode External interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related external interrupts cannot be used). External interrupts INT0-INT1 in the S3C9454B/F9454B interrupt structure meet this criteria.

  • Page 127: Hardware Reset Values

    RESET and POWER-DOWN S39454B/F9454B HARDWARE RESET VALUES Table 8-1 lists the values for CPU and system registers, peripheral control registers, and peripheral data registers following a Reset operation in normal operating mode. — A "1" or a "0" shows the Reset bit value as logic one or logic zero, respectively. —...
  • Page 128 S39454B/F9454B RESET and POWER-DOWN Table 8-1. Register Values After a Reset (Continued) Register Name Mnemonic Address Bit Values After RESET Port 0 data register – – – – Port 1 data register – Port 2 data register – Locations E3H–E5H are not mapped Port 0 control register (High byte) P0CONH Port 0 control register...
  • Page 129 RESET and POWER-DOWN S39454B/F9454B PROGRAMMING TIP — Sample S3C9454B/F9454B Initialization Routine ;--------------<< Interrupt Vector Address >> 0000H VECTOR 00H,INT_9454 ; S3C9454B/F9454B has only one interrupt vector ;--------------<< Smart Option >> 003CH ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 0E7H ;...
  • Page 130 S39454B/F9454B RESET and POWER-DOWN PROGRAMMING TIP — Sample S3C9454B/F9454B Initialization Routine (Continued) ;--------------<< Main loop >> MAIN: ; Start main loop BTCON,#02H ; Enable watchdog function ; Basic counter (BTCNT) clear • • CALL KEY_SCAN • • • CALL LED_DISPLAY •...
  • Page 131 RESET and POWER-DOWN S39454B/F9454B PROGRAMMING TIP — Sample S3C9454B/F9454B Initialization Routine (Continued) ;--------------<< Interrupt Service Routines >> ; Interrupt enable bit and pending bit check INT_9454: T0CON,#00000010B ; Timer0 interrupt enable check Z,NEXT_CHK1 T0CON,#00000001B ; If timer0 interrupt was occurred, NZ,INT_TIMER0 ;...
  • Page 132 S39454B/F9454B RESET and POWER-DOWN PROGRAMMING TIP — Sample S3C9454B/F9454B Initialization Routine (Continued) ;--------------< External interrupt0 service routine > • INT0_INT: • P0PND,#11111110B ; INT0 Pending bit clear IRET ; Interrupt return ;--------------< External interrupt1 service routine > • INT1_INT: •...
  • Page 133 RESET and POWER-DOWN S39454B/F9454B NOTES 8-10...

  • Page 134: Chapter 9 I/O Ports

    I/O PORTS OVERVIEW The S3C9454B/F9454B has three I/O ports: with 18 pins total. You access these ports directly by writing or reading port data register addresses. All ports can be configured as LED drive. (High current output: typical 10 mA) Table 9-1.

  • Page 135: Port Data Registers

    I/O PORTS S3C9454B/F9454B PORT DATA REGISTERS Table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics. Data registers for ports 0-2 have the structure shown in Figure 9-1. Table 9-2. Port Data Register Summary...
  • Page 136 S3C9454B/F9454B I/O PORTS PORT 0 Port 0 is a bit-programmable, general-purpose, I/O ports. You can select normal input or push-pull output mode. In addition, you can configure a pull-up resistor to individual pins using control register settings. It is designed for high-current functions such as LED direct drive. Part 0 pins can also be used as alternative functions (ADC input, external interrupt input and PWM output).

  • Page 137: Port 0

    I/O PORTS S3C9454B/F9454B Port 0 Control Register (High Byte) E6H, R/W [.7-.6] Port, P0.7/ADC7 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = A/D converter input (ADC7); schmitt trigger input off [.5-.4] Port 0, P0.6/ADC6/PWM Configuration Bits...
  • Page 138 S3C9454B/F9454B I/O PORTS Port 0 Control Register (Low Byte) E7H, R/W [.7-.6] Port 0, P0.3/ADC3 Configuration Bits 0 0 = Schmitt trigger input 0 1 = Schmitt trigger input; pull-up enable 1 0 = Push-pull output 1 1 = A/D converter input (ADC3); Schmitt trigger input off [.5-.4] Port 0, P0.2/ADC2 Configuration Bits...
  • Page 139 I/O PORTS S3C9454B/F9454B Port 0 Interrupt Pending Register E8H, R/W [.7-.4] Not used for S3C9454B/F9454B [.3] Port 0.1/ADC1/INT1, Interrupt Enable Bit 0 = INT1 falling edge interrupt disable 1 = INT1 falling edge interrupt enable [.2] Port 0.1/ADC1/INT1, Interrupt Pending Bit...

  • Page 140: Port 1

    S3C9454B/F9454B I/O PORTS PORT 1 Port 1, is a 3-bit I/O port with individually configurable pins. It can be used for general I/O port (Schmitt trigger input mode, push-pull output mode or n-channel open-drain output mode). In addition, you can configure a pull-up and pull-down resistor to individual pin using control register settings.
  • Page 141 [.6] Port 1.0 N-Channel Open-Drain Enable Bit 0 = Configure P1.0 as a push-pull output 1 = Configure P1.0 as a N-channel open-drain output [.5-.4] Not used for S3C9454B/F9454B [.3-.2] Port 1, P1.1 Configuration Bits 0 0 = Schmitt trigger input;...
  • Page 142 S3C9454B/F9454B I/O PORTS PORT 2 Port 2 is a 7-bit I/O port with individually configurable pins. It can be used for general I/O port (schmitt trigger input mode, push-pull output mode or N-channel open-drain output mode). You can also use some pins of port 2 ADC input, CLO output and T0 clock output.

  • Page 143: Port 2

    I/O PORTS S3C9454B/F9454B Port 2 Control Register (High Byte) EAH, R/W [.7] Not sued for S3C9454B/F9454B [.6-.4] Port 2, P2.6/ADC8/CLO Configuration Bits 0 0 0 = Schmitt trigger input; pull-up enable 0 0 1 = Schmitt trigger input 0 1 x = ADC input 1 0 0 = Push-pull output 1 0 1 = Open-drain output;...
  • Page 144 S3C9454B/F9454B I/O PORTS Port 2 Control Register (Low Byte) EBH, R/W [.7-.6] Port 2, P2.3 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = Open-drain output [.5-.4] Port 2, P2.2 Configuration Bits...
  • Page 145 I/O PORTS S3C9454B/F9454B NOTES 9-12...

  • Page 146: Module Overview

    BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 MODULE OVERVIEW The S3C9454B/F9454B has two default timers: an 8-bit basic timer, one 8-bit general-purpose timer/counter, called timer 0. Basic Timer (BT) You can use the basic timer (BT) in two different ways: —...

  • Page 147: Basic Timer (Bt)

    BASIC TIMER and TIMER 0 S3C9454B/F9454B BASIC TIMER (BT) BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function.

  • Page 148: Basic Timer Function Description

    S3C9454B/F9454B BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a Reset by setting BTCON.7–BTCON.4 to any value other than "1010B" (The "1010B" value disables the watchdog function). A Reset clears BTCON to "00H", automatically enabling the watchdog timer function.
  • Page 149 BASIC TIMER and TIMER 0 S3C9454B/F9454B Oscillation Stabilization Time Normal Operating mode 0.8 V Reset Release Voltage RESET trst Internal Reset Release 0.8 V Oscillator Oscillator Stabilization Time BTCNT clock 10000B BTCNT value 00000B = (4096x16)/f WAIT Basic timer increment and...
  • Page 150 S3C9454B/F9454B BASIC TIMER and TIMER 0 Normal STOP Mode Oscillation Stabilization Time Normal Operating Operating Mode Mode STOP Instruction STOP Mode Execution Release Signal External Interrupt RESET STOP Release Signal Oscillator BTCNT clock 10000B BTCNT 00000B Value WAIT Basic Timer Increment...
  • Page 151 This example shows how to configure the basic timer to sample specification. 0000H VECTOR 00H,INT_9454 ; S3C9454B/F9454B has only one interrupt vector ;--------------<< Smart Option >> 003CH ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 0E7H ;...

  • Page 152: Timer 0

    1 = Interrupt is pending (when read) 11 = fosc 1 = No effect (when write) Timer 0 interrupt enable bit: Not used for S3C9454B/F9454B 0 = Disable T0 interrupt 1 = Enable T0 interrupt Not used for S3C9454B/F9454B Timer 0 counter clear bit:...

  • Page 153: Timer 0 Function Description

    BASIC TIMER and TIMER 0 S3C9454B/F9454B TIMER 0 FUNCTION DESCRIPTION Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the Timer 0 reference data register, T0DATA. The match signal generates a Timer 0 match interrupt (T0INT, vector 00H) and then clears the counter.
  • Page 154 S3C9454B/F9454B BASIC TIMER and TIMER 0 Match Match Match Compare Value (T0DATA) Match Match Match Match Up Counter Value (T0CNT) Clear Clear Clear Count start T0CON.3 1 T0DATA Value change Counter Clear (T0CON.3) Interrupt Request (T0CON.0) T0 Match Output (P2.0) Figure 10-6.
  • Page 155 BASIC TIMER and TIMER 0 S3C9454B/F9454B Bit 1 RESET or STOP Basic Timer Control Register Bits 3, 2 (Write '1010xxxxB' to disable.) Data Bus Clear 1/4096 8-Bit Up Counter RESET 1/1024 (BTCNT, Read-Only) 1/128 When BTCNT.4 is set after releasing from RESET or STOP mode, CPU clock starts.
  • Page 156 PROGRAMMING TIP1 – Configuring Timer 0 (Interval Mode) The following sample program sets Timer 0 to interval timer mode. 0000H VECTOR 00H,INT_9454 ; S3C9454B/F9454B has only one interrupt vector 003CH ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 0E7H ;...
  • Page 157 BASIC TIMER and TIMER 0 S3C9454B/F9454B PROGRAMMING TIP1 – Configuring Timer 0 (Interval Mode) (Continued) LED_DISPLAY: • • • JOB: • • • ;--------------<< Interrupt Service Routines >> INT_9454: T0CON,#00000010B ; Interrupt enable check Z,NEXT_CHK1 T0CON,#00000001B ; If timer 0 interrupt was occurred, NZ,INT_TIMER0 ;...

  • Page 158: 8-Bit Pwm

    S3C9454B/F9454B 8-BIT PWM 8-BIT PWM (PULSE WIDTH MODULATION OVERVIEW This microcontroller has the 8-bit PWM circuit. The operation of all PWM circuit is controlled by a single control register, PWMCON. The PWM counter is a 8-bit incrementing counter. It is used by the 8-bit PWM circuits. To start the counter and enable the PWM circuits, you set PWMCON.2 to "1".
  • Page 159 8-BIT PWM S3C9454B/F9454B PWM Data and Extension Registers PWM (duty) data registers, located in F2H, determine the output value generated by each 8-bit PWM circuit. To program the required PWM output, you load the appropriate initialization values into the 6-bit reference data register (PWMDATA.7–.2) and the 2-bit extension data register (PWMDATA.1–.0).
  • Page 160 S3C9454B/F9454B 8-BIT PWM Table 11-2. PWM output "stretch" Values for Extension Data Register (PWMDATA.1–.0) PWMDATA Bit (Bit1–Bit0) "Stretched" Cycle Number – 1, 3 1, 2, 3 4 MHz Clock: 000000xxB 250 ns 250 ns 000001xxB Data Register Values: 100000xxB (PWMDATA)
  • Page 161 8-BIT PWM S3C9454B/F9454B PWM Clock: 4 MHz 500 ns 000010xxB PWMDATA : 0000 1001B Basic Extended waveform waveform 1st 2nd 3th 1st 2nd 3th 4 MHz 750 ns Figure 11-2. 8-Bit Extended PWM Waveform 11-4...

  • Page 162: Pwm Control Register (Pwmcon)

    S3C9454B/F9454B 8-BIT PWM PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is located at register address F3H. PWMCON is used the 8- bit PWM modules. Bit settings in the PWMCON register control the following functions: — PWM counter clock selection —...
  • Page 163 8-BIT PWM S3C9454B/F9454B PWMCON.6-.7 From 8-bit up counter (7:6) From 8-bit up counter (5:0) 2-bit 6-bit Counter Counter PWMCON.2 "1" When REG > Count 6-bit Comparator P0.6/PWM "1" When REG = Count 6-bit Data Buffer Extension Control Logic Extension Data...
  • Page 164 S3C9454B/F9454B 8-BIT PWM PROGRAMMING TIP — Programming the PWM Module to Sample Specifications ;--------------<< Interrupt Vector Address >> 0000H VECTOR 00H,INT_9454 ; S3C9454/F9454 has only one interrupt vector ;--------------<< Smart Option >> 003CH ; 003CH, must be initialized to 0.
  • Page 165 8-BIT PWM S3C9454B/F9454B PROGRAMMING TIP — Programming the PWM Module to Sample Specifications (Continued) INT_PWM: ; PWM interrupt service routine • • • PWMCON,#11110110B ; pending bit clear IRET • • 11-8...

  • Page 166: Chapter 12 A/D Converter

    S3C9454B/F9454B A/D CONVERTER A/D CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the nine input channels to equivalent 10-bit digital values. The analog input level must lie between the V and V values.

  • Page 167: Using A/D Pins For Standard Digital Input

    A/D CONVERTER S3C9454B/F9454B USING A/D PINS FOR STANDARD DIGITAL INPUT The ADC module's input pins are alternatively used as digital input in port 0 and P2.6. A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address F7H. ADCON has four functions: —...

  • Page 168: Internal Reference Voltage Levels

    S3C9454B/F9454B A/D CONVERTER INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range V to V Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step.

  • Page 169: Conversion Timing

    A/D CONVERTER S3C9454B/F9454B ADC0N.0 50 ADC clock Conversion Start ADDATA ADDATAH (8-bit) + ADDATAL (2-bit) Privious Valid Value data Set-up time 40 clock 10 clock Figure 12-4. A/D Converter Timing Diagram CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up A/D conversion.

  • Page 170: Internal A/D Conversion Procedure

    S3C9454B/F9454B A/D CONVERTER INTERNAL A/D CONVERSION PROCEDURE 1. Analog input must remain between the voltage range of V and V 2. Configure the analog input pins to input mode by making the appropriate settings in P0CONH, P0CONL and P2CONH registers.
  • Page 171 A/D CONVERTER S3C9454B/F9454B PROGRAMMING TIP – Configuring A/D Converter 0000H VECTOR 00H,INT_9454 ; S3C9454/F9454 has only one interrupt vector 003CH ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 0E7H ; 003EH, enable LVR (2.3 V) ;...
  • Page 172 S3C9454B/F9454B A/D CONVERTER PROGRAMMING TIP – Configuring A/D Converter (Continued) CONV_LOOP: TM ADCON,#00001000B ; Check EOC flag Z,CONV_LOOP ; If EOC flag=0, jump to CONV_LOOP until EOC flag=1 R0,ADDATAH ; High 8 bits of conversion result are stored ; to ADDATAH register R1,ADDATAL ;...
  • Page 173 A/D CONVERTER S3C9454B/F9454B NOTES 12-8...

  • Page 174: Electrical Data

    S3C9454B/F9454B ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the following S3C9454B/F9454B electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Input timing measurement points — Oscillator characteristics —...
  • Page 175 ELECTRICAL DATA S3C9454B/F9454B Table 13-1. Absolute Maximum Ratings = 25 °C) Parameter Symbol Conditions Rating Unit Supply voltage – – 0.3 to + 6.5 – 0.3 to V + 0.3 Input voltage All ports – 0.3 to V + 0.3...
  • Page 176 S3C9454B/F9454B ELECTRICAL DATA Table 13-2. DC Electrical Characteristics = – 25 °C to + 85 °C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit = 2.0 to 5.5 V 0.8 V Input high Ports 0, 1, 2 and –...
  • Page 177 ELECTRICAL DATA S3C9454B/F9454B Table 13-3. AC Electrical Characteristics = – 25 °C to + 85 °C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Interrupt input – – INT0, INT1 INTL = 5 V ± 10 %...
  • Page 178 S3C9454B/F9454B ELECTRICAL DATA Table 13-4. Oscillator Characteristics = – 25 °C to + 85 °C) Oscillator Clock Circuit Test Condition Unit = 4.5 to 5.5 V Main crystal or – ceramic = 2.7 to 4.5 V – = 2.0 to 2.7 V –...
  • Page 179 ELECTRICAL DATA S3C9454B/F9454B CPU Clock 10 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1 MHz Supply Voltage (V) Figure 13-2. Operating Voltage Range A = 0.2 V B = 0.4 V C = 0.6 V D = 0.8 V 0.3 V...
  • Page 180 S3C9454B/F9454B ELECTRICAL DATA Table 13-6. Data Retention Supply Voltage in Stop Mode = – 25 °C to + 85 °C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Data retention Stop mode – DDDR supply voltage Stop mode; V = 2.0 V...
  • Page 181 ELECTRICAL DATA S3C9454B/F9454B Table 13-7. A/D Converter Electrical Characteristics = – 25 °C to + 85 °C, V = 2.0 V to 5.5 V, V = 0 V) Parameter Symbol Test Conditions Unit ± 3 = 5.12 V Total accuracy –...
  • Page 182 S3C9454B/F9454B ELECTRICAL DATA Table 13-8. LVR Circuit Characteristics = 25 °C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Low voltage reset – LVR,MAX LVR,MIN Figure 13-5. LVR Reset Timing 13-9...
  • Page 183 ELECTRICAL DATA S3C9454B/F9454B NOTES 13-10...

  • Page 184: Mechanical Data

    MECHANICAL DATA OVERVIEW The S3C9454B/F9454B is available in a 20-pin DIP package (Samsung: 20-DIP-300A), a 20-pin SOP package (Samsung: 20-SOP-375), a 20-pin SSOP package (Samsung: 20-SSOP-225), a 16-pin DIP package (Samsung: 16-DIP-300A), a 16-pin SOP package (Samsung: 16-SOP-BD300-SG), a 16-pin SSOP package (Samsung: 16- SSOP-BD44).
  • Page 185 MECHANICAL DATA S3C9454B/F9454B 20-SOP-375 + 0.10 0.203 - 0.05 13.14 MAX ± 0.20 12.74 0.10 MAX 1.27 (0.66) + 0.10 0.40 - 0.05 NOTE: Dimensions are in millimeters. Figure 14-2. 20-SOP-375 Package Dimensions 14-2...
  • Page 186 S3C9454B/F9454B MECHANICAL DATA 20-SSOP-225 + 0.10 0.15 - 0.05 6.90 MAX ± 0.20 6.50 0.10 MAX (0.30) 0.65 +0.10 0.22 -0.05 NOTE: Dimensions are in millimeters. Figure 14-3. 20-SSOP-225 Package Dimensions 14-3...
  • Page 187 MECHANICAL DATA S3C9454B/F9454B 0-15 16-DIP-300A 19.80 MAX ± 0.20 19.40 ± 0.10 0.46 2.54 ± 0.10 (0.81) 1.50 NOTE: Dimensions are in millimeters. Figure 14-4. 16-DIP-300A Package Dimensions 14-4...
  • Page 188 S3C9454B/F9454B MECHANICAL DATA 10.50 10.10 0.30 0.10 16-SOP-BD300-SG 0.32 0.23 1.27 0.40 0.75 × 45 ° 0.50 2.65 2.35 1.27BSC 0.48 0.35 NOTE: Dimensions are in millimeters. Figure 14-5. 16-SOP-BD300-SG Package Dimensions 14-5...
  • Page 189 MECHANICAL DATA S3C9454B/F9454B 16-SSOP-BD44 +0.10 0.15 -0.05 +0.004 0.006 -0.002 ± 0.10 6.50 ± 0.004 0.256 0.10 MAX 0.80 0.004 MAX 0.45 0.031 0.018 +0.10 0.30 -0.07 +0.004 0.012 -0.003 NOTE: Dimensions are in millimeters. Figure 14-6. 16-SSOP-BD44 Package Dimensions...

  • Page 190: Overview

    S3C9454B/F9454B S3F9454B MTP S3F9454B MTP OVERVIEW The S3F9454B single-chip CMOS microcontroller is the MTP (Multi Time Programmable) version of the S3C9454BB/F9454B microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format.
  • Page 191 S3F9454B MTP S3C9454B/F9454B /P1.0 P0.0/ADC0/INT0/SCL /P1.1 P0.1/ADC1/INT1/SDA /RESET/P1.2 P0.2/ADC2 S3F9454B T0/P2.0 P0.3/ADC3 P2.1 P0.4/ADC4 P0.5/ADC5 P2.2 P0.6/ADC6/PWM P2.3 NOTE: The bolds indicate MTP pin name. Figure 15-2. Pin Assignment Diagram (16-Pin Package) 15-2...

  • Page 192: Operating Mode Characteristics

    5 V is applied, MTP is in reading mode. (Option) 20 (20-pin), 16 (16-pin) Logic power supply pin. 1 (20-pin), 1 (16-pin) Table 15-2. Comparison of S3F9454B and S3C9454B Features Characteristic S3F9454B S3C9454B Program memory 4 Kbyte Flash ROM...
  • Page 193 S3F9454B MTP S3C9454B/F9454B NOTES 15-4...

  • Page 194: Development Tools

    S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2, and SK-1000 is supported by a third party tool vendor. Samsung also offers support software that includes debugger, assembler, and a program for setting options.

  • Page 195: Target Boards

    Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. MTPs Multi times programmable microcontrollers (MTPs) are under development for S3C9454B/F9454B microcontroller. IBM-PC AT or Compatible RS-232C Emulator (SMDS2+ or SK-1000)

  • Page 196: Tb9454B Target Board

    S3C9454B/F9454B DEVELOPMENT TOOLS TB9454B TARGET BOARD The TB9454B target board is used for the S3C9454B/F9454B microcontrollers. It is supported by the SK1000/SMDS2+ development systems. TB9454B To User_V RESET Idle Stop J101 128 QFP S3E9450 EVA Chip External 8 pin DIP switch...
  • Page 197 DEVELOPMENT TOOLS S3C9454B/F9454B Table 16-1. Power Selection Settings for TB9454B "To User_Vcc" Settings Operating Mode Comments The SK1000/SMDS2+ main To user_Vcc board supplies V to the External TB9454B Target target board (evaluation chip) System and the target system. SK-1000/SMDS2+ The SK1000/SMDS2+ main...
  • Page 198 S3C9454B/F9454B DEVELOPMENT TOOLS Table 16-3. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments Connector from External External Trigger Triggers Sources of the Application System You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SK-1000/SMDS2+ breakpoint and trace functions.
  • Page 199 P2.1 P0.4/ADC4 P2.2 P0.5/ADC5 P2.3 P0.6/ADC6/PWM P2.4 P0.7/ADC7 P2.5 P2.6/ADC8/CLO Figure 16-4. 20-Pin Connector for TB9454B Target Board Target System J101 Part Name: AS20D Order Cods: SM6304 10 11 10 11 Figure 16-5. S3C9454B/F9454B Probe Adapter for 20-DIP Package 16-6...

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