Pwmdl — Comparator0 Output Delay Register: F5H, Bank0 - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
4.1.31 PWMDL — COMPARATOR0 OUTPUT DELAY REGISTER: F5H, BANK0
Bit Identifier
RESET Value
Read/Write
Addressing Mode
.7–.4
.3–.0
NOTE: 0 < TST（setting time）< 4/fpwmclk
4.1.32 PP — REGISTER PAGE POINTER: DFH, BANK0
Bit Identifier
Reset Value
Read/Write
.7–.0
NOTE: In S3F84B8, only Page 0 settings are valid. Register page pointer values for the source and destination register page
are automatically set to '00F' following a hardware reset. These values should not be changed during normal
operation.
.7 .6
– –
– –
Register addressing mode only
Not used for S3F84B8.
Delay Time = (PWMDL+1)4/fpwmclk + TST
.7 .6
0 0
R/W R/W
Not used for S3F84B8.
.5 .4
– –
– – R/W
.5 .4
0 0
R/W R/W R/W
4-31
4 CONTROL REGISTERS
.3 .2 .1
0 0
R/W R/W
.3 .2 .1
0 0 0
R/W R/W
.0
0 0
R/W
.0
0
R/W