Interrupt Priority Register (Ipr) - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

5.1.11 INTERRUPT PRIORITY REGISTER (IPR)

The interrupt priority register, IPR (FFH, Set1, Bank0), is used to set the relative priorities of interrupt levels in the
microcontroller's interrupt structure. After a reset, all IPR bit values are undetermined and must be written to their
required settings by the initialization routine.
When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two
sources belong to the same interrupt level, the source with lower vector address has priority (This priority is fixed
in the hardware).
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by
the interrupt logic.
NOTE: These groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see
Group A
Group B
Group C
IRQ0
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.
For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B"
would select the relationship C > B > A.
The functions of other IPR bit settings are as follows:

IPR.5 controls the relative priorities of group C interrupts.

Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5,
6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C.

IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.
IRQ0, IRQ1
IRQ2, IRQ3, IRQ4
IRQ5, IRQ6, IRQ7
IPR
Group A
A1 A2
IRQ1 IRQ2
Figure 5-7
IPR
Group B
B1 B2
B21 B22
IRQ3 IRQ4
Interrupt Request Priority Groups
5-10
5 INTERRUPT STRUCTURE
Figure
IPR
Group C
C1 C2
C21 C22
IRQ5 IRQ6 IRQ7
5-7):