System Clock Control Register (Clkcon) - Samsung S3F80P5X User Manual

CLOCK AND POWER CIRCUITS

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in address D4H, Set1, Bank0. It is read/write addressable
and has the following functions:
— Oscillator frequency divide-by value
The CLKCON.7– .5 and CLKCON.2- .0 Bit are not used in S3F80P5. After a reset, the main oscillator is activated,
and the f (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the
OSC/16
CPU clock speed to f
OSC
7-4
, f , f or f
OSC/2 OSC/8 OSC/16
System Clock Control Register (CLKCON)
D4H, Set 1, Bank 0, R/W
MSB .7 .6 .5
Not used
Figure 7-4. System Clock Control Register (CLKCON)
.
.4 .3 .2 .1
Not used
Divide-by selection bits for
CPU clock frequency
00 = fosc/16
01 = fosc/8
10 = fosc/2
11 = fosc (non-divided)
S3F80P5_UM_ REV1.00
.0 LSB