Pwm Cmp Linkage Control Register (Pwmccon) - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

16.2.5 PWM CMP LINKAGE CONTROL REGISTER (PWMCCON)

The control register for linkage of CMP and PWM module, PWMCCON, is located at register address F0H, Set 1,
Bank 0.
Bit settings in the PWMCCON register control the linkage configuration of PWM CMP0, PWM CMP1, PWM
CMP2, and PWM CMP3.
A reset clears all the PWMCCON bits to logic zero, disabling the entire linkage.
MSB
CMP3 PWM trigger mode :
X0 = disable linkage
01 = Soft lock
11 = hard lock
MSB
MSB
PWM Control Registers (PWMCCON)
F0H, Set 1, Bank 0, Reset=00H, R/W
.7 .6 .5
CMP2 PWM trigger mode :
X0 = disable linkage
01 = Soft lock
11 = hard lock
Figure 16-2 PWM CMP Linkage Control Register (PWMCCON)
Anti-mis-trigger Data Registers (AMTDATA )
F6H, Set 1, Bank 0, Reset=00H, R/W
.7 .6 .5
Anti-mis-trigger time = (AMTDATA x 4)/fpwmclk + T
0 < T
NOTE:
ST
Figure 16-3 Anti-mis-trigger Data Register (AMTDATA)
PWM Delay trigger Registers (PWMDL)
F5H, Set 1, Bank 0, Reset=00H, R/W
- - - -
Delay Time = (PWMDL+1)x 4/fpwmclk + T
0 <T (Setting time ) < 4/fpwmclk
NOTE:
ST
Figure 16-4
.4 .3 .2
CMP1 PWM trigger mode :
X0 = disable linkage
01 = Soft lock
11 = hard lock
.4 .3 .2 .1
(setting time ) < 4/fpwmclk
.3 .2 .1
Delay trigger Data Register (PWMDL)
16-5
.1 .0 LSB
CMP0 PWM trigger mode :
X0 = Disable linkage
01 = Normal trigger
11 = Delay trigger
.0 LSB
ST
.0 LSB
ST
16 10-BIT IH-PWM