Tacon — Timer A Control Register: E1H, Bank1 - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
4.1.39 TACON — TIMER A CONTROL REGISTER: E1H, BANK1
Bit Identifier
RESET Value
Read/Write
.7–.6
.5
.4
.3
.2
.1
.0
.7 .6
0 0
R/W R/W
Timer A Operating Mode Selection Bits
0 0 Internal mode (TAOUT mode)
0 1 Capture mode (captures on rising edge; counter running; OVF can occur)
1 0 Capture mode (captures on falling edge; counter running; OVF can occur)
1 1 PWM mode (OVF interrupt can occur)
Timer A Counter Clear Bit
0 No effect.
1 Clears the timer A counter (After clearing, returns to zero).
Timer A Start/Stop Bit
0 Stops Timer A.
1 Starts Timer A.
Timer A Match/Capture Interrupt Enable Bit
0 Disables interrupt.
1 Enables interrupt.
Timer A Overflow Interrupt Enable Bit
0 Disables interrupt.
1 Enables interrupt.
Timer A Match Interrupt Pending Bit
0 No interrupt is pending; clears pending bit (when write).
1 Interrupt is pending.
Timer A Overflow Interrupt Pending Bit
0 No interrupt is pending; clears pending bit (when write).
1 Interrupt is pending.
.5 .4
0 0
R/W R/W R/W
4-36
4 CONTROL REGISTERS
.3 .2 .1
0 0 0
R/W R/W
.0
0
R/W