Samsung S3F84B8 User Manual page 13

Figure 13-1 A/D Converter Control Register (ADCON) ................................................................................... 13-2
Figure 13-2 A/D Converter Circuit Diagram ..................................................................................................... 13-3
Figure 13-3 A/D Converter Data Register (ADDATAH/L) ................................................................................ 13-3
Figure 13-4 A/D Converter Timing Diagram..................................................................................................... 13-4
Figure 13-5 Recommended A/D Converter Circuit for Highest Absolute Accuracy......................................... 13-5
CMP0 Control Register (CMP0CON) ........................................................................................... 14-2
Figure 14-1
Figure 14-2 CMP Interrupt Mode Control Register (CMPINT) ......................................................................... 14-2
Figure 14-3 Block Diagram of Comparator 0 ................................................................................................... 14-3
Figure 14-4 CMP1 Control Register (CMP1CON) ........................................................................................... 14-5
Figure 14-5 CMP2 Control Register (CMP2CON) ........................................................................................... 14-5
Figure 14-6 CMP3 Control Register (CMP3CON) ........................................................................................... 14-6
Figure 14-7 CMP Interrupt Mode Control Register (CMPINT) ......................................................................... 14-6
Figure 14-8 Block Diagram of Comparator 1/2/3 ............................................................................................. 14-7
Figure 15-1 OPAMP Control Register (OPACON)........................................................................................... 15-2
Figure 15-2 Block Diagram of OPAMP ............................................................................................................ 15-2
Figure 15-3 OPAMP Application Reference Circuit @ Gain=10...................................................................... 15-3
Figure 16-1 PWM Module Control Register (PWMCON)................................................................................. 16-4
Figure 16-2 PWM CMP Linkage Control Register (PWMCCON) .................................................................... 16-5
Figure 16-3 Anti-mis-trigger Data Register (AMTDATA).................................................................................. 16-5
Figure 16-4 Delay trigger Data Register (PWMDL) ......................................................................................... 16-5
Figure 16-5 Functional Block Diagram of PWM Module .................................................................................. 16-6
Figure 16-6 Example of the cooperation of PWM and Comparator 0_Delay Trigger ...................................... 16-7
Figure 16-7 Example of the cooperation of PWM and Comparator 0_Anti-mis-Trigger .................................. 16-7
Figure 16-8 Example of the Cooperation of PWM and Comparator 1/2/3_ Hard Lock ................................... 16-8
Figure 16-9 Example of the Cooperation of PWM and Comparator 1/2/3_Soft Lock ...................................... 16-8
Figure 17-1 Buzzer Control Register (BUZCON) ............................................................................................. 17-1
Figure 17-2 BUZ Functional Block Diagram..................................................................................................... 17-3
Figure 18-1 Pin Assignment Diagram (20-Pin SOP/DIP Package) ................................................................. 18-1
Figure 19-1 Smart Option................................................................................................................................. 19-2
Figure 19-2 Flash Memory Control Register (FMCON) ................................................................................... 19-3
Figure 19-3 Flash Memory User Programming Enable Register (FMUSR)..................................................... 19-3
Figure 19-4 Flash Memory Sector Address Register (FMSECH) .................................................................... 19-4
Figure 19-5 Flash Memory Sector Address Register (FMSECL)..................................................................... 19-4
Figure 19-6 Sector configurations in User Program Mode............................................................................... 19-5
Figure 19-7 Sector Erase Flowchart in User Program Mode ........................................................................... 19-6
Figure 19-8 Byte Program Flowchart in a User Program Mode....................................................................... 19-9
Figure 19-9 Program Flowchart in a User Program Mode ............................................................................. 19-10
Figure 20-1 Low Voltage Reset Circuit ............................................................................................................ 20-2
Figure 21-1 Input Timing Measurement Points ................................................................................................ 21-4
Figure 21-2 Operating Voltage Range @ External clock ................................................................................. 21-7
Figure 21-3 Schmitt Trigger Input Characteristics Diagram............................................................................. 21-7
Figure 21-4 Stop Mode Release Timing When Initiated by a RESET ............................................................. 21-8
Figure 21-5 LVR Reset Timing....................................................................................................................... 21-11
Figure 21-6 Circuit Diagram to Improve the EFT Characteristics .................................................................. 21-12