Basic Timer Function Description - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00

10.2.1 BASIC TIMER FUNCTION DESCRIPTION

10.2.1.1 Watchdog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to
any value other than "1010B". (The "1010B" value disables the watchdog function.)
A reset clears BTCON to "00H", automatically enabling the watchdog timer function. It also selects the oscillator
clock divided by 4096 as the BT clock.
A reset occurs whenever a basic timer counter overflows. During normal operation, the application program must
prevent the overflow and its accompanying reset operation from occurring. To do this, the BTCNT value must be
cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or other error condition, the BT counter clear operation will not
be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the
basic timer overflow loop (a bit 7 overflow of 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear
instruction. If a malfunction occurs, a reset is triggered automatically.
10.2.1.2 Oscillation Stabilization Interval Timer Function
You can use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop
mode has been released by an external interrupt.
In the Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then
starts increasing at the rate of f
When BTCNT.7 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the
clock signal off to the CPU so that it can resume normal operation.
In summary, the following events occur when Stop mode is released:
1. During Stop mode, an external power-on reset or an external interrupt occurs to trigger the Stop mode
release, leading to the start of oscillation.
2. If external power-on reset occurs, the basic timer counter will increase at the rate of fOSC/4096. If an external
interrupt releases the Stop mode, the BTCNT value increases at the rate of preset clock source.
3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set.
4. When a BTCNT.7 is set, normal CPU operation is resumed.
and
Figure 10-3
Figure 10-2
/4096 (for reset), or at the rate of preset clock source (for an external interrupt).
OSC
show the oscillation stabilization time on RESET and STOP mode release.
10-3
10 BASIC TIMER