Register Set 1 - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES

2.3.1.1 Register Set 1

The term set 1 refers to the upper 64 bytes of register file in locations C0H–FFH.
The upper 32 byte area of this 64 byte space (E0H–FFH) is expanded into two 32 byte register banks, bank 0 and
bank 1. The set register bank instructions, SB0 or SB1, are used to address one of the banks. A hardware reset
operation always selects bank 0 addressing.
The upper two 32 byte areas (bank 0 and bank 1) of set 1 (E0H–FFH) contains 46 mapped system and peripheral
control registers. The lower 32 byte area contains 14 system registers (D0H–DFH) and a 16 byte common
working register area (C0H–CFH). You can use the common working register area as a "scratch" area for data
operations being performed in other areas of the register file.
Using the Register Addressing mode, the registers in set 1 location can be directly accessed at any time. The 16
byte working register area can only be accessed using working register addressing (For more information about
working register addressing, refer to Chapter 3, "Addressing Modes").
2.3.1.2 Register Set 2
The same 64 byte physical space that is used for set 1 location C0H–FFH is logically duplicated to add another 64
bytes of register space. This expanded area of the register file is called set 2. For S3F84B8, the set 2 address
range (C0H–FFH) is accessible on page 0 only. (S3F84B8 has only implemented page 0.)
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only
Register addressing mode to access set 1 location. In order to access registers in set 2, you must use Register
Indirect addressing mode or Indexed addressing mode.
Set 2 register area is commonly used for stack operations.
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