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Samsung S3F80P5X User Manual

S3f80p5 microcontrollers
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USER'S MANUAL
S3F80P5X
S3F80P5 MICROCONTROLLERS
April 2010
REV 1.00
Confidential Proprietary of Samsung Electronics Co., Ltd
Copyright © 2009 Samsung Electronics, Inc. All Rights Reserved

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Summary of Contents for Samsung S3F80P5X

  • Page 1 USER’S MANUAL S3F80P5X S3F80P5 MICROCONTROLLERS April 2010 REV 1.00 Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2009 Samsung Electronics, Inc. All Rights Reserved...

  • Page 2: Important Notice

    Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...

  • Page 3: Part I Programming Model

    Two order forms are included at the back of this manual to facilitate customer order for S3F80P5 microcontroller: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.

  • Page 4: Table Of Contents

    Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8/S3F8-Series Microcontrollers......................1-1 S3F80P5 Microcontroller..........................1-1 Features ................................1-2 CPU.................................1-2 Memory ..............................1-2 Instruction Set ............................1-2 Instruction Execution Time ........................1-2 Interrupts ..............................1-2 I/O Ports ..............................1-2 Carrier Frequency Generator........................1-2 Basic Timer and Timer/Counters ......................1-2 Back-up Mode............................1-2 Low Voltage Detect Circuit ........................1-2 Operating Temperature Range.......................1-2...
  • Page 5 Table of Contents (Continued) Chapter 3 Addressing Modes Overview ............................... 3-1 Register Addressing Mode (R) ....................... 3-2 Indirect Register Addressing Mode (IR) ....................3-3 Indexed Addressing Mode (X)........................ 3-7 Direct Address Mode (DA) ........................3-10 Direct Address MODE (Continued) ......................3-11 Indirect Address Mode (IA)........................
  • Page 6 Table of Contents (Continued) Chapter 6 Instruction Set Overview................................6-1 Data Types..............................6-1 Register Addressing..........................6-1 Addressing Modes ..........................6-1 Flags Register (FLAGS) .........................6-6 Flag Descriptions ............................6-7 Instruction Set Notation...........................6-8 Condition Codes .............................6-12 Instruction Descriptions ..........................6-13 Chapter 7 Clock and Power Circuit Overview................................7-1 System Clock Circuit..........................7-1 Clock Status During Power-Down Modes ....................7-3 System Clock Control Register (CLKCON) ....................7-4 Chapter 8...
  • Page 7 Table of Contents (Continued) Hardware Descriptions Part II Chapter 9 I/O Ports Overview ............................... 9-1 Port Data Registers ..........................9-3 Pull-Up Resistor Enable Registers ......................9-4 Chapter 10 Basic timer and Timer 0 Overview ............................... 10-1 Basic Timer (BT)............................. 101 Timer 0..............................
  • Page 8 Table of Contents (Continued) Chapter 12 Counter A Overview................................12-1 Counter A Control Register (CACON) ....................12-3 Counter A Pulse Width Calculations.......................12-4 Chapter 13 Timer 2 Overview................................13-1 Timer 2 Overflow Interrupt ........................13-2 Timer 2 Capture Interrupt ........................13-2 Timer 2 Match Interrupt...........................13-3 Timer 2 Control Register (T2CON) ......................13-5 Chapter 14 Embedded Flash Memory Interface Overview................................14-1...
  • Page 9 Table of Contents (Conclude) Chapter 15 Lower Voltage Detector Overview ............................... 15-1 LVD................................. 15-1 LVD FLAG .............................. 15-1 Low Voltage Detector Control Register (LVDCON) ................15-4 Low Voltage Detector Flag Selection Register (LVDSEL) ..............15-4 Chapter 16 Electrical Data 16.1 Overview ............................... 16-1 Chapter 17 Mechanical 17.1 Overview ...............................
  • Page 11 List of Figures Figure Title Page Number Number Block Diagram (24-pin) ....................1-3 Pin Assignment Diagram (24-Pin SOP/SDIP Package) ..........1-4 Pin Circuit Type 1 (Port 0) ..................1-6 Pin Circuit Type 2 (Port 1) ..................1-7 Pin Circuit Type 2 (Port 2) ..................1-8 Pin Circuit Type 4 (P3.0) ....................
  • Page 12 List of Figures (Continued) Figure Title Page Number Number S3C8/S3F8-Series Interrupt Types ................5-2 S3F80P5 Interrupt Structure..................5-3 ROM Vector Address Area ..................5-4 Interrupt Function Diagram..................5-7 System Mode Register (SYM) ..................5-9 Interrupt Mask Register (IMR) ..................5-10 Interrupt Request Priority Groups................5-11 Interrupt Priority Register (IPR) ..................5-12 Interrupt Request Register (IRQ) ................5-13 System Flags Register (FLAGS) ................6-6 Main Oscillator Circuit (External Crystal or Ceramic Resonator) ......7-2...
  • Page 13 List of Figures (Conclude) Figure Title Page Number Number 12-1 Counter A Block Diagram................... 12-2 12-2 Counter A Control Register (CACON) ............... 12-3 12-3 Counter A Registers ....................12-3 12-4 Counter A Output Flip-Flop Waveforms in Repeat Mode .......... 12-5 13-1 Simplified Timer 2 Function Diagram: Capture Mode ..........

  • Page 15: Overview

    List of Tables Table Title Page Number Number Pin Descriptions of 24-SOP/SDIP ................1-5 The Summary of S3F80P5 Register Type ..............2-5 Mapped Registers (Bank0, Set1) ................4-2 Mapped Registers (Continued) .................. 4-3 Mapped Registers (Bank1, Set1) ................4-4 Each Function Description and Pin Assignment of P3CON in 24 Pin Package ..4-33 S3F80P5 Interrupt Vectors..................
  • Page 16 List of Tables(Conclude) Table Title Page Number Number 18-1 Descriptions of Pins Used to Read/Write the Flash ROM..........18-3 18-2 Operating Mode Selection Criteria ................18-4 19-1 Components of TB80PB.....................19-4 19-2 Setting of the Jumper in TB80PB ................19-5 S3F80P5_UM_REV1.00 MICROCONTROLLER...

  • Page 17: Chapter 1 Product Overview

    S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8/S3F8-SERIES MICROCONTROLLERS Samsung's S3C8/S3F8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various flash memory ROM sizes. Important CPU features include: • Efficient register-oriented architecture •...

  • Page 18: Features

    PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 FEATURES Back-up Mode • SAM8 RC CPU core • When V is lower than V LVD is ‘ON’ and the LVD, chip enters Back-up mode to block oscillation Memory • Program memory: - 18-Kbyte Internal Flash Memory Low Voltage Detect Circuit - 10 years data retention •...

  • Page 19: Block Diagram (24-Pin Package)

    S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW BLOCK DIAGRAM (24-PIN PACKAGE) Figure 1-1. Block Diagram (24-pin)

  • Page 20: Pin Assignments

    PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN ASSIGNMENTS P2.0/INT5 P3.1/REM/T0CK Xout P3.0/T0PWM/T0CAP/T1CAP/T2CAP TEST S3C80P5 P1.7 SDAT/P0.0/INT0 P1.6 SCLK/P0.1/INT1 P1.5 nRESET/P0.2/INT2 24-SOP/SDIP P1.4 P0.3/INT3 (TOP VIEW) P1.3 P0.4/INT4 P1.2 P0.5/INT4 P1.1 P0.6/INT4 P1.0 P0.7/INT4 Figure 1-2. Pin Assignment Diagram (24-Pin SOP/SDIP Package)
  • Page 21 S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW Table 1-1. Pin Descriptions of 24-SOP/SDIP Circuit 28 Pin Shared Pin Description Names Type Type Functions I/O port with bit-programmable pins. Configurable 5-12 Ext. INT P0.0−P0.7 to input or push-pull output mode. Pull-up resistors (INT0−INT3) are assignable by software. Pins can be assigned (INT4) individually as external interrupt inputs with noise (SDAT)

  • Page 22: Pin Circuits

    PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN CIRCUITS Pull-Up Resistor (67kΩ- typ) Pull-up Enable Data INPUT/OUTPUT Output Disable External Noise Interrupt Filter Stop Stop Release Figure 1-3. Pin Circuit Type 1 (Port 0)
  • Page 23 S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW PIN CIRCUITS (Continued) Pull-up Resistor (67kΩ-Typ) Pull-up Enable Data INPUT/OUTPUT Open-Drain Output Disable Normal Noise Input Filter Figure 1-4. Pin Circuit Type 2 (Port 1)
  • Page 24 PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN CIRCUITS (Continued) Pull-Up Resistor (67kΩ- typ) Pull-up Enable Data INPUT/ OUTPUT Open-Drain Output Disable External Noise Interrupt Filter Figure 1-5. Pin Circuit Type 2 (Port 2)
  • Page 25 S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW PIN CIRCUITS (Continued) Pull-up Resistor (67kΩ-Typ) Pull-up Enable P3CON.2 Port 3.0 Data Data T0_PWM P3.0/T0PWM/T0CAP/ T1CAP/T2CAP Open-Drain Output Disable P3.0 Input P3CON.2,6,7 T0CAP/T1CAP/T2CAP Noise filter Figure 1-6. Pin Circuit Type 4 (P3.0)
  • Page 26 PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN CIRCUITS (Continued) Pull-up Resistor (67kΩ-Typ) Pull-up Enable P3CON.5 Port 3.1 Data Data Carrier On/Off (P3DAT.7) CACON.2 P3.1/REM/T0CK Open-Drain Output Disable P3.1 Input P3CON.5,6,7 T0CK Noise filter Figure 1-7. Pin Circuit Type 5 (P3.1) 1-10...

  • Page 27: Overview

    S3F80P5_UM_ REV1.00 ADDRESS SPACE ADDRESS SPACE OVERVIEW The S3F80P5 microcontroller has two types of address space: — Internal program memory (Flash memory) — Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file.

  • Page 28: Program Memory

    ADDRESS SPACE S3F80P5_UM_ REV1.00 PROGRAM MEMORY Program memory stores program code or table data. The S3F80P5 has 18-Kbyte of internal programmable Flash memory. The program memory address range is therefore 0000H–47FFH of Flash memory (See Figure 2-1). The first 256 bytes of the program memory (0H–0FFH) are reserved for interrupt vector addresses. Unused locations (0000H –...

  • Page 29: Smart Option

    S3F80P5_UM_ REV1.00 ADDRESS SPACE SMART OPTION Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80P5 only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH).
  • Page 30 ADDRESS SPACE S3F80P5_UM_ REV1.00 NOTES 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless. 2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H).

  • Page 31: Register Architecture

    S3F80P5_UM_ REV1.00 ADDRESS SPACE REGISTER ARCHITECTURE In the S3F80P5 implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area.
  • Page 32 ADDRESS SPACE S3F80P5_UM_ REV1.00 Set 1 Set 2 Bank1 Bank 0 Page 0 System and Bytes Peripheral Control Register (Register Addressing General Purpose Mode) Data Register Bytes (Indirect Register or System Register Indexed Addressing (Register Addressing Modes or Mode) Stack Operations) Bytes Bytes Working Register...

  • Page 33: Register Page Pointer (Pp)

    S3F80P5_UM_ REV1.00 ADDRESS SPACE REGISTER PAGE POINTER (PP) The S3C8/S3F8-series architecture supports the logical expansion of the physical 333-byte internal register files (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer PP (DFH, Set 1, and Bank0). In the S3F80P5 microcontroller, a paged register file expansion is not implemented and the register page pointer settings therefore always point to “page 0”.

  • Page 34: Register Set 1

    ADDRESS SPACE S3F80P5_UM_ REV1.00 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two 32-byte register banks, bank 0 and bank 1.

  • Page 35: Prime Register Space

    S3F80P5_UM_ REV1.00 ADDRESS SPACE PRIME REGISTER SPACE The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) are called the prime register space or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.).

  • Page 36: Working Registers

    ADDRESS SPACE S3F80P5_UM_ REV1.00 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of 32 8-byte register groups or "slices."...

  • Page 37: Using The Register Pointers

    S3F80P5_UM_ REV1.00 ADDRESS SPACE USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
  • Page 38 ADDRESS SPACE S3F80P5_UM_ REV1.00 F7H (R7) 8-Byte Slice F0H (R0) Register File Contains 32 16-byte non-contiguous 8-Byte Slices working register block 1 1 1 1 0 X X X 07H (R15) 0 0 0 0 0 X X X 8-Byte Slice 00H (R0) Figure 2-8.

  • Page 39: Register Addressing

    S3F80P5_UM_ REV1.00 ADDRESS SPACE REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access all locations in the register file except for set 2.
  • Page 40 ADDRESS SPACE S3F80P5_UM_ REV1.00 Special-Purpose Registers General-Purpose Registers Bank 1 Bank 0 Control Registers Set 2 System Registers Register Pointers Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2).

  • Page 41: Common Working Register Area (C0H-Cfh)

    S3F80P5_UM_ REV1.00 ADDRESS SPACE COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area.

  • Page 42: Example 1

    ADDRESS SPACE S3F80P5_UM_ REV1.00 PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Example 1: 0C2H,40H ; Invalid addressing mode! Use working register addressing instead: #0C0H ;...
  • Page 43 S3F80P5_UM_ REV1.00 ADDRESS SPACE Selects RP0 or RP1 Address OPCODE 4-bit address procides three Register pointer low-order bits provides five high-order bits Together they create an 8-bit register address Figure 2-12. 4-Bit Working Register Addressing 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0...

  • Page 44: 8-Bit Working Register Addressing

    ADDRESS SPACE S3F80P5_UM_ REV1.00 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100B.
  • Page 45 S3F80P5_UM_ REV1.00 ADDRESS SPACE 0 1 1 1 0 0 0 0 0 0 0 Selects RP1 8-bit address from instruction 'LD R11, R2' Specifies working register addressing Register address (0ABH) 1 0 1 Figure 2-15. 8-Bit Working Register Addressing Example 2-19...

  • Page 46: System And User Stacks

    ADDRESS SPACE S3F80P5_UM_ REV1.00 SYSTEM AND USER STACKS S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3F80P5 architecture supports stack operations in the internal register file.
  • Page 47 S3F80P5_UM_ REV1.00 ADDRESS SPACE PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SPL ← FFH SPL,#0FFH ; (Normally, the SPL is set to 0FFH by the initialization ;...
  • Page 48 ADDRESS SPACE S3F80P5_UM_ REV1.00 NOTES 2-22...

  • Page 49: Chapter 3 Addressing Modes

    S3F80P5_UM_ REV1.00 ADDRESSING MODES ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memory for execution. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.

  • Page 50: Register Addressing Mode (R)

    ADDRESSING MODES S3F80P5_UM_ REV1.00 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing because it uses a register pointer to specify an 8- byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).

  • Page 51: Indirect Register Addressing Mode (Ir)

    S3F80P5_UM_ REV1.00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).
  • Page 52 ADDRESSING MODES S3F80P5_UM_ REV1.00 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Register Example Pair Instruction Points to References OPCODE Register Pair Program 16-Bit Memory Address Points to Program Program Memory Memory Sample Instructions: Value used in OPERAND instruction CALL @RR2 @RR2...
  • Page 53 S3F80P5_UM_ REV1.00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points Program Memory to start of woking register 4-bit block 3 LSBs Working Register Point to the OPCODE ADDRESS Address Woking Register...
  • Page 54 ADDRESSING MODES S3F80P5_UM_ REV1.00 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register 4-bit Working block Register Address Register Next 2-bit Point Pair OPCODE to Working Example Instruction...

  • Page 55: Indexed Addressing Mode (X)

    S3F80P5_UM_ REV1.00 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3–7). You can use Indexed addressing mode to access locations in the internal register file or in external memory (if implemented).
  • Page 56 ADDRESSING MODES S3F80P5_UM_ REV1.00 INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register block OFFSET NEXT 2 BITS 4-bit Working dst/src Register Register Address Point to Working Pair OPCODE...
  • Page 57 S3F80P5_UM_ REV1.00 ADDRESSING MODES INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of Program Memory working register OFFSET block OFFSET NEXT 2 BITS 4-bit Working dst/src Register Register Address Point to Working Pair OPCODE...

  • Page 58: Direct Address Mode (Da)

    ADDRESSING MODES S3F80P5_UM_ REV1.00 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.

  • Page 59: Direct Address Mode (Continued)

    S3F80P5_UM_ REV1.00 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16-bit immediate address CALL DISPLAY Where DISPLAY is a 16-bit immediate address Figure 3-11.

  • Page 60: Indirect Address Mode (Ia)

    ADDRESSING MODES S3F80P5_UM_ REV1.00 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.

  • Page 61: Relative Address Mode (Ra)

    S3F80P5_UM_ REV1.00 ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.

  • Page 62: Immediate Mode (Im)

    ADDRESSING MODES S3F80P5_UM_ REV1.00 IMMEDIATE MODE (IM) In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.

  • Page 63: Chapter 4 Control Registers

    S3F80P5_UM_ REV1.00 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3F80P5 control registers are presented in an easy-to-read format. You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.
  • Page 64 CONTROL REGISTERS S3F80P5_UM_ REV1.00 Table 4-1. Mapped Registers (Bank0, Set1) Register Name Mnemonic Decimal (NOTE) Timer 0 Counter T0CNT Timer 0 Data Register T0DATA Timer 0 Control Register T0CON Basic Timer Control Register BTCON Clock Control Register CLKCON System Flags Register FLAGS Register Pointer 0 Register Pointer 1...
  • Page 65 S3F80P5_UM_ REV1.00 CONTROL REGISTERS Table 4-1. Mapped Registers (Continued) Register Name Mnemonic Decimal Counter A Control Register CACON Counter A Data Register (High Byte) CADATAH Counter A Data Register (Low Byte) CADATAL (NOTE) Timer 1 Counter Register (High Byte) T1CNTH (NOTE) Timer 1 Counter Register (Low Byte) T1CNTL...
  • Page 66 CONTROL REGISTERS S3F80P5_UM_ REV1.00 Table 4-2. Mapped Registers (Bank1, Set1) Register Name Mnemonic Decimal LVD Control Register LVDCON Reserved E1H Reserved E2H Reserved E3H (NOTE) Timer 2 Counter Register (High Byte) T2CNTH (NOTE) Timer 2 Counter Register (Low Byte) T2CNTL Timer 2 Data Register (High Byte) T2DATAH Timer 2 Data Register (Low Byte)
  • Page 67 S3F80P5_UM_ REV1.00 CONTROL REGISTERS Bit number(s) that is/are appended to the Register address register name for bit addressing (Set ) Name of individual Register address Register address Register bit or bit function (Hexadecimal) (Bank ) Full register name mnemonic Set1 Bank0 FLAGS - System Flags Register...
  • Page 68 CONTROL REGISTERS S3F80P5_UM_ REV1.00 BTCON — Basic Timer Control Register D3H Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7− .4 Watchdog Timer Function Enable Bits (for System Reset) Disable watchdog timer function Any other value Enable watchdog timer function .3 and .2 Basic Timer Input Clock Selection Bits...
  • Page 69 S3F80P5_UM_ REV1.00 CONTROL REGISTERS CACON — Counter A Control Register Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7 and .6 Counter A Input Clock Selection Bits .5 and .4 Counter A Interrupt Timing Selection Bits Elapsed time for Low data value Elapsed time for High data value Elapsed time for combined Low and High data values...
  • Page 70 CONTROL REGISTERS S3F80P5_UM_ REV1.00 CLKCON — System Clock Control Register D4H Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7− .5 Not used for S3F80P5 .4 and .3 CPU Clock (System Clock) Selection Bits (non-divided) .2–...
  • Page 71 S3F80P5_UM_ REV1.00 CONTROL REGISTERS (NOTE) — External Memory Timing Register FEH Set1 Bank0 Bit Identifier − Reset Value − Read/Write Addressing Mode Register addressing mode only External WAIT Input Function Enable Bit Disable WAIT input function for external device Enable WAIT input function for external device Slow Memory Timing Enable Bit Disable slow memory timing Enable slow memory timing...
  • Page 72 CONTROL REGISTERS S3F80P5_UM_ REV1.00 FLAGS — System Flags Register D5H Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Carry Flag Bit (C) Operation does not generate a carry or borrow condition Operation generates a carry-out or borrow into high-order bit 7 Zero Flag Bit (Z) Operation result is a non-zero value Operation result is zero...
  • Page 73 S3F80P5_UM_ REV1.00 CONTROL REGISTERS FMCON — Flash Memory Control Register EFH Set1 Bank1 Bit Identifier − − − Reset Value − − − Read/Write Addressing Mode Register addressing mode only Flash Memory Mode Selection Bits .7− .4 0101 Programming mode 1010 Erase mode (NOTE)
  • Page 74 CONTROL REGISTERS S3F80P5_UM_ REV1.00 FMSECH — Flash Memory Sector Address Register(High Byte) ECH Set1 Bank1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Flash Memory Sector Address (High Byte) .7− .0 Note: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address.
  • Page 75 S3F80P5_UM_ REV1.00 CONTROL REGISTERS — Interrupt Mask Register DDH Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4 Disable (mask) Enable (un-mask) Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0 Disable (mask) Enable (un-mask) Not used for S3F80P5...
  • Page 76 CONTROL REGISTERS S3F80P5_UM_ REV1.00 — Instruction Pointer (High Byte) DAH Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Instruction Pointer Address (High Byte) .7− .1 The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8).
  • Page 77 S3F80P5_UM_ REV1.00 CONTROL REGISTERS — Interrupt Priority Register Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C Group priority undefined B > C > A A >...
  • Page 78 CONTROL REGISTERS S3F80P5_UM_ REV1.00 — Interrupt Request Register DCH Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4 Not pending Pending Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0 Not pending Pending Not used for S3F80P5...
  • Page 79 S3F80P5_UM_ REV1.00 CONTROL REGISTERS LVDCON — LVD Control Register Set1 Bank1 Bit Identifier − − − − − − − Reset Value − − − − − − − Read/Write Addressing Mode Register addressing mode only .7− .1 Not used for S3F80P5. LVD Flag Indicator Bit LVD_FLAG Level DD ≥...
  • Page 80 CONTROL REGISTERS S3F80P5_UM_ REV1.00 LVDSEL — LVD Flag Level Selection Register Set1 Bank1 Bit Identifier − − − − − − Reset Value − − − − − − Read/Write Addressing Mode Register addressing mode only .7 and .6 LVD Flag Level Selection Bits LVD_FLAG Level = 1.88V LVD_FLAG Level = 1.98V LVD_FLAG Level = 2.53V...
  • Page 81 S3F80P5_UM_ REV1.00 CONTROL REGISTERS P0CONH — Port 0 Control Register (High Byte) Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7 and .6 P0.7/INT4 Mode Selection Bits C-MOS input mode; interrupt on falling edges C-MOS input mode; interrupt on rising and falling edges Push-pull output mode C-MOS input mode;...
  • Page 82 CONTROL REGISTERS S3F80P5_UM_ REV1.00 P0CONL — Port 0 Control Register (Low Byte) Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7 and .6 P0.3/INT3 Mode Selection Bits C-MOS input mode; interrupt on falling edges C-MOS input mode; interrupt on rising and falling edges Push-pull output mode C-MOS input mode;...
  • Page 83 S3F80P5_UM_ REV1.00 CONTROL REGISTERS P0INT — Port 0 External Interrupt Enable Register Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only P0.7 External Interrupt (INT4) Enable Bit Disable interrupt Enable interrupt P0.6 External Interrupt (INT4) Enable Bit Disable interrupt Enable interrupt P0.5 External Interrupt (INT4) Enable Bit...
  • Page 84 CONTROL REGISTERS S3F80P5_UM_ REV1.00 P0PND — Port 0 External Interrupt Pending Register Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only P0.7 External Interrupt (INT4) Pending Flag Bit (see Note) No P0.7 external interrupt pending (when read) P0.7 external interrupt is pending (when read) P0.6 External Interrupt (INT4) Pending Flag Bit No P0.6 external interrupt pending (when read)
  • Page 85 S3F80P5_UM_ REV1.00 CONTROL REGISTERS P0PUR — Port 0 Pull-up Resistor Enable Register Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only P0.7 Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P0.6 Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P0.5 Pull-up Resistor Enable Bit...
  • Page 86 CONTROL REGISTERS S3F80P5_UM_ REV1.00 P1CONH — Port 1 Control Register (High Byte) EAH Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7 and .6 P1.7 Mode Selection Bits C-MOS input mode Open-drain output mode Push-pull output mode C-MOS input with pull up mode .5 and .4 P1.6 Mode Selection Bits...
  • Page 87 S3F80P5_UM_ REV1.00 CONTROL REGISTERS P1CONL — Port 1 Control Register (Low Byte) EBH Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7 and .6 P1.3 Mode Selection Bits C-MOS input mode Open-drain output mode Push-pull output mode C-MOS input with pull up mode .5 and .4 P1.2 Mode Selection Bits...
  • Page 88 CONTROL REGISTERS S3F80P5_UM_ REV1.00 P1OUTPU — Port 1 Output Pull-up Resistor Enable Register Set1 Bank1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only P1.7 Output Mode Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P1.6 Output Mode Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P1.5 Output Mode Pull-up Resistor Enable Bit...
  • Page 89 S3F80P5_UM_ REV1.00 CONTROL REGISTERS P2CONL — Port 2 Control Register (Low Byte) EDH Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .1 and .0 P2.0/INT5 Mode Selection Bits C-MOS input mode; interrupt on falling edges C-MOS input mode;...
  • Page 90 CONTROL REGISTERS S3F80P5_UM_ REV1.00 P2INT — Port 2 External Interrupt Enable Register Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only P2.0 External Interrupt (INT4) Enable Bit Disable interrupt Enable interrupt 4-28...
  • Page 91 S3F80P5_UM_ REV1.00 CONTROL REGISTERS P2OUTMD — Port 2 Output Mode Selection Register Set1 Bank1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only P2.0 Output Mode Selection Bit Push-pull output mode Open-drain output mode 4-29...
  • Page 92 CONTROL REGISTERS S3F80P5_UM_ REV1.00 P2PND — Port 2 External Interrupt Pending Register Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only P2.0 External Interrupt (INT4) Pending Flag Bit No P2.0 external interrupt pending (when read) P2.0 external interrupt is pending (when read) NOTE: To clear an interrupt pending condition, write a “0”...
  • Page 93 S3F80P5_UM_ REV1.00 CONTROL REGISTERS P2PUR — Port 2 Pull-up Resistor Enable Register EEH Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only P2.0 Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor 4-31...
  • Page 94 CONTROL REGISTERS S3F80P5_UM_ REV1.00 P3CON — Port 3 Control Register EFH Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7 and .6 Package Selection and Alternative Function Select Bits 24 pin package P3.0: T0PWM/T0CAP/T1CAP, P3.1: REM/ T0CK Others Not used for S3F80P5 P3.1 Function Selection Bit...
  • Page 95 S3F80P5_UM_ REV1.00 CONTROL REGISTERS NOTES: The port 3 data register, P3, at location E3H, set1, bank0, contains seven bit values which correspond to the following Port 3 pin functions (bit 6 is not used for the S3F80P5) a. Port3, bit 7: carrier signal on (“1”) or off (“0”). b.
  • Page 96 CONTROL REGISTERS S3F80P5_UM_ REV1.00 P3OUTPU — Port 3 Output Pull-up Resistor Enable Register Set1 Bank1 Bit Identifier − − − − − − Reset Value − − − − − − Read/Write Addressing Mode Register addressing mode only .7 and .2 Not used for S3F80P5 P3.1 Output Mode Pull-up Resistor Enable Bit Disable pull-up resistor...
  • Page 97 S3F80P5_UM_ REV1.00 CONTROL REGISTERS — Register Page Pointer DFH Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Destination Register Page Selection Bits .7− .4 (See Note) Destination: page 0 Source Register Page Selection Bits .3− .0 (See Note) Source: page 0 NOTE: In the S3F80P5 microcontroller, a paged expansion of the internal register file is not implemented.
  • Page 98 CONTROL REGISTERS S3F80P5_UM_ REV1.00 RESETID — Reset Source Indicating Register Set1 Bank1 Bit Identifier − − − Read/Write Addressing Mode Register addressing mode only Not used for S3F80P5. .7− .4 Key-in Reset Indicating Bit Reset is not generated by P0, P2 external INT Reset is generated by P0, P2 external INT WDT Reset Indicating Bit Reset is not generated by WDT (when read)
  • Page 99 S3F80P5_UM_ REV1.00 CONTROL REGISTERS — Register Pointer 0 D6H Set1 Bank0 Bit Identifier − − − Reset Value − − − Read/Write Addressing Mode Register addressing mode only Register Pointer 0 Address Value .7− .3 Register pointer 0 can independently point to one of the 248-byte working register areas in the register file.
  • Page 100 CONTROL REGISTERS S3F80P5_UM_ REV1.00 — Stack Pointer (Low Byte) D9H Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only. Stack Pointer Address (Low Byte) .7− .0 The SP value is undefined following a reset. STOPCON — Stop Control Register FBH Set1 Bank0 Bit Identifier Reset Value...
  • Page 101 S3F80P5_UM_ REV1.00 CONTROL REGISTERS — System Mode Register DEH Set1 Bank0 Bit Identifier − − Reset Value − − Read/Write Addressing Mode Register addressing mode only (note1) Tri-State External Interface Control Bit Normal operation (disable tri-state operation) Set external interface lines to high impedance (enable tri-state operation) (note2) .6 and .5 Not used for S3F80P5...
  • Page 102 CONTROL REGISTERS S3F80P5_UM_ REV1.00 T0CON — Timer 0 Control Register Set 1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only Timer 0 Input Clock Selection Bits .7− .6 /4096 /256 External clock input (at the T0CK pin, P3.1 or P3.2) .5 and .4 Timer 0 Operating Mode Selection Bits Interval timer mode (counter cleared by match signal)
  • Page 103 S3F80P5_UM_ REV1.00 CONTROL REGISTERS T1CON — Timer 1 Control Register FAH Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7 and .6 Timer 1 Input Clock Selection Bits Internal clock (counter A flip-flop, T-FF) .5 and .4 Timer 1 Operating Mode Selection Bits Interval timer mode (counter cleared by match signal) Capture mode (rising edges, counter running, OVF can occur)
  • Page 104 ADDRESSING MODES S3F80P5_UM_ REV1.00 T2CON − Timer 2 Control Register Set1 Bank1 Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7 and .6 Timer 2 Input Clock Selection Bits Internal clock (counter A flip-flop, T-FF) .5 and .4 Timer 2 Operating Mode Selection Bits Interval timer mode (counter cleared by match signal) Capture mode (rising edges, counter running, OVF can occur)

  • Page 105: Chapter 5 Interrupt Structure

    S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8/S3F8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources.

  • Page 106: Interrupt Types

    INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT TYPES The three components of the S3C8/S3F8-series interrupt structure described above — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic.
  • Page 107 S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE Levels(7) Vectors(14) Sources(17) Reset/Clear 100H RESET Basic timer overflow Timer 0 match/capture IRQ0 Timer 0 overflow Timer 1 match/capture IRQ1 Timer 1 overflow IRQ2 Counter A Timer 2 match/capture IRQ3 Timer 2 overflow IRQ4 P2.0 external interrupt P0.3 external interrupt P0.2 external interrupt IRQ6...

  • Page 108: Interrupt Vector Addresses

    INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3F80P5 interrupt structure are stored in the vector address area of the internal program memory ROM, 00H−FFH (See Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
  • Page 109 S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE Table 5-1. S3F80P5 Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Interrupt Priority in Value Value Level Level − √ 100H Basic timer overflow/POR RESET √ Timer 0 match/capture IRQ0 √ Timer 0 overflow √ Timer 1 match/capture IRQ1 √...

  • Page 110: Enable/Disable Interrupt Instructions (Ei, Di)

    INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur, and according to the established priorities. NOTE The system initialization routine that is executed following a reset must always contain an EI instruction to globally enable the interrupt structure.

  • Page 111: Interrupt Processing Control Points

    S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by a specific interrupt level and source. The system-level control points in the interrupt structure are, therefore: • Global interrupt enable and disable (by EI and DI instructions or by a direct manipulation of SYM.0) •...

  • Page 112: Peripheral Interrupt Control Registers

    INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (See Table 5-3). Table 5-3. Vectored Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register(s)

  • Page 113: System Mode Register (Sym)

    S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE SYSTEM MODE REGISTER (SYM) The system mode register, SYM (DEH, Set 1, Bank0), is used to globally enable and disable interrupt processing and to control fast interrupt processing (See Figure 5-5). A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value, SYM.4−SYM.2, is for fast interrupt level selection and undetermined values after reset.

  • Page 114: Interrupt Mask Register (Imr)

    INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set 1, and Bank0) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.

  • Page 115: Interrupt Priority Register (Ipr)

    S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (FFH, Set 1, Bank 0), is used to set the relative priorities of the interrupt levels used in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
  • Page 116 INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 Interrupt Priority Register(IPR) FEH, Set 1, Bank 0 , R/W Group Priority: Group A 0 = IRQ0 > IRQ1 D7 D4 D1 1 = IRQ0 < IRQ1 Group B = Undefined 0 = IRQ2 > (IRQ3, IRQ4) = B >...

  • Page 117: Interrupt Request Register (Irq)

    S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (DCH, Set 1, Bank0), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on.

  • Page 118: Interrupt Pending Function Types

    INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other type must be cleared by the interrupt service routine. Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1"...

  • Page 119: Interrupt Source Polling Sequence

    S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source. 3.

  • Page 120: Generating Interrupt Vector Addresses

    INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (except smart option ROM Cell- 003CH, 003DH, 003EH and 003FH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1.

  • Page 121: Fast Interrupt Processing (Continued)

    S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING (Continued) Two other system registers support fast interrupt processing: • The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the program counter values), and •...
  • Page 122 INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 NOTES 5-18...

  • Page 123: Chapter 6 Instruction Set

    S3F80P5_UM_ REV1.00 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: —...
  • Page 124 INSTRUCTION SET S3F80P5_UM_ REV1.00 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst, src Load dst, src Load bit dst, src Load external data memory dst, src Load program memory LDED dst, src Load external data memory and decrement LDCD dst, src Load program memory and decrement...
  • Page 125 S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions dst,src Add with carry dst,src dst,src Compare Decimal adjust Decrement DECW Decrement word dst,src Divide Increment INCW Increment word MULT dst,src Multiply dst,src Subtract with carry dst,src Subtract Logic Instructions...
  • Page 126 INSTRUCTION SET S3F80P5_UM_ REV1.00 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL Call procedure CPIJE dst,src Compare, increment and jump on equal CPIJNE dst,src Compare, increment and jump on non-equal...
  • Page 127 S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic SWAP Swap nibbles CPU Control Instructions Complement carry flag Disable interrupts Enable interrupts IDLE...

  • Page 128: Flags Register (Flags)

    INSTRUCTION SET S3F80P5_UM_ REV1.00 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic.

  • Page 129: Flag Descriptions

    S3F80P5_UM_ REV1.00 INSTRUCTION SET FLAG DESCRIPTIONS Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.

  • Page 130: Instruction Set Notation

    INSTRUCTION SET S3F80P5_UM_ REV1.00 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation –...
  • Page 131 S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Bit (b) of working register Rn.b (n = 0–15, b = 0–7) Bit 0 (LSB) of working register Rn (n = 0–15) Working register pair...
  • Page 132 INSTRUCTION SET S3F80P5_UM_ REV1.00 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1.b, R2 BXOR r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb SRP/0/1 BTJR IRR1 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM...
  • Page 133 S3F80P5_UM_ REV1.00 INSTRUCTION SET Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – DJNZ NEXT r1,R2 r2,R1 r1,RA cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ ↓ ENTER EXIT IDLE ↓ ↓ ↓ ↓ ↓ ↓ ↓...

  • Page 134: Condition Codes

    INSTRUCTION SET S3F80P5_UM_ REV1.00 CONDITION CODES The op-code of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal.

  • Page 135: Instruction Descriptions

    S3F80P5_UM_ REV1.00 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...
  • Page 136 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Add with Carry dst,src dst ← dst + src + c Operation: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed.
  • Page 137 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the most significant bit of the result;...
  • Page 138 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...
  • Page 139 S3F80P5_UM_ REV1.00 INSTRUCTION SET BAND — Bit AND BAND dst,src.b BAND dst.b,src dst(0) ← dst(0) AND src(b) Operation: dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source).
  • Page 140 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Bit Compare dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.
  • Page 141 S3F80P5_UM_ REV1.00 INSTRUCTION SET BITC — Bit Complement BITC dst.b dst(b) ← NOT dst(b) Operation: This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0".
  • Page 142 INSTRUCTION SET S3F80P5_UM_ REV1.00 BITR — Bit Reset BITR dst.b dst(b) ← 0 Operation: The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex)
  • Page 143 S3F80P5_UM_ REV1.00 INSTRUCTION SET BITS — Bit Set BITS dst.b dst(b) ← 1 Operation: The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex)
  • Page 144 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Bit OR dst,src.b dst.b,src dst(0) ← dst(0) OR src(b) Operation: dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected.
  • Page 145 S3F80P5_UM_ REV1.00 INSTRUCTION SET BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b If src(b) is a "0", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...
  • Page 146 INSTRUCTION SET S3F80P5_UM_ REV1.00 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b If src(b) is a "1", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...
  • Page 147 S3F80P5_UM_ REV1.00 INSTRUCTION SET BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src dst(0) ← dst(0) XOR src(b) Operation: dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected.
  • Page 148 INSTRUCTION SET S3F80P5_UM_ REV1.00 CALL — Call Procedure CALL ← Operation: SP – 1 ← ← SP –1 ← ← The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
  • Page 149 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented.
  • Page 150 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Clear dst ← "0" Operation: The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: →...
  • Page 151 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set;...
  • Page 152 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Compare dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow"...
  • Page 153 S3F80P5_UM_ REV1.00 INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA If dst – src = "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter.
  • Page 154 INSTRUCTION SET S3F80P5_UM_ REV1.00 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA If dst – src "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...
  • Page 155 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Decimal Adjust dst ← DA dst Operation: The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed.
  • Page 156 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Decimal Adjust (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH R1,R0 R1 ←...
  • Page 157 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred;...
  • Page 158 INSTRUCTION SET S3F80P5_UM_ REV1.00 DECW — Decrement Word DECW dst ← dst – 1 Operation: The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. Flags: C: Unaffected.
  • Page 159 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Disable Interrupts SYM (0) ← 0 Operation: Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
  • Page 160 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Divide (Unsigned) dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination.
  • Page 161 S3F80P5_UM_ REV1.00 INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst r ← r – 1 Operation: If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.
  • Page 162 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Enable Interrupts SYM (0) ← 1 Operation: An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
  • Page 163 S3F80P5_UM_ REV1.00 INSTRUCTION SET ENTER — Enter ENTER SP ← SP – 2 Operation: ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer.
  • Page 164 INSTRUCTION SET S3F80P5_UM_ REV1.00 EXIT — Exit EXIT IP ← @SP Operation: SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.
  • Page 165 S3F80P5_UM_ REV1.00 INSTRUCTION SET IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected.
  • Page 166 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred;...
  • Page 167 S3F80P5_UM_ REV1.00 INSTRUCTION SET INCW — Increment Word INCW dst ← dst + 1 Operation: The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Unaffected.
  • Page 168 INSTRUCTION SET S3F80P5_UM_ REV1.00 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) FLAGS ← @SP PC ↔ IP Operation: SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine.
  • Page 169 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.
  • Page 170 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...
  • Page 171 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc src | opc r = 0 to F dst | src...
  • Page 172 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Load (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0 = 10H LD R0,#10H →...
  • Page 173 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Load Bit dst,src.b dst.b,src dst(0) ← src(b) Operation: dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected.
  • Page 174 INSTRUCTION SET S3F80P5_UM_ REV1.00 LDC/LDE — Load Memory LDC/LDE dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory.
  • Page 175 S3F80P5_UM_ REV1.00 INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: R0 ←...
  • Page 176 INSTRUCTION SET S3F80P5_UM_ REV1.00 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
  • Page 177 S3F80P5_UM_ REV1.00 INSTRUCTION SET LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
  • Page 178 INSTRUCTION SET S3F80P5_UM_ REV1.00 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src rr ← rr – 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented.
  • Page 179 S3F80P5_UM_ REV1.00 INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src rr ← rr + 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented.
  • Page 180 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Load Word dst,src dst ← src Operation: The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Examples:...
  • Page 181 S3F80P5_UM_ REV1.00 INSTRUCTION SET MULT — Multiply (Unsigned) MULT dst,src dst ← dst × src Operation: The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.
  • Page 182 INSTRUCTION SET S3F80P5_UM_ REV1.00 NEXT — Next NEXT PC ← @ IP Operation: IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.
  • Page 183 S3F80P5_UM_ REV1.00 INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycles...
  • Page 184 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...
  • Page 185 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.
  • Page 186 INSTRUCTION SET S3F80P5_UM_ REV1.00 POPUD — Pop User Stack (Decrementing) POPUD dst,src dst ← src Operation: IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.
  • Page 187 S3F80P5_UM_ REV1.00 INSTRUCTION SET POPUI — Pop User Stack (Incrementing) POPUI dst,src dst ← src Operation: IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.
  • Page 188 INSTRUCTION SET S3F80P5_UM_ REV1.00 PUSH — Push To Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.
  • Page 189 S3F80P5_UM_ REV1.00 INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src IR ← IR – 1 Operation: dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.
  • Page 190 INSTRUCTION SET S3F80P5_UM_ REV1.00 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src IR ← IR + 1 Operation: dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.
  • Page 191 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: Given: C = "1"...
  • Page 192 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
  • Page 193 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
  • Page 194 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Rotate Left Through Carry dst (0) ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...
  • Page 195 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
  • Page 196 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Rotate Right Through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...
  • Page 197 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Select Bank 0 BANK ← 0 Operation: The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected.
  • Page 198 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Select Bank 1 BANK ← 1 Operation: The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3F8-series microcontrollers.) Flags: No flags are affected.
  • Page 199 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Subtract With Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
  • Page 200 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: The statement...
  • Page 201 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.
  • Page 202 INSTRUCTION SET S3F80P5_UM_ REV1.00 SRP/SRP0/SRP1 — Set Register Pointer SRP0 SRP1 ← Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) src (3–7) ← If src (1) = 0 and src (0) = 1 then: RP1 (3–7) src (3–7) ←...
  • Page 203 S3F80P5_UM_ REV1.00 INSTRUCTION SET STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.
  • Page 204 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
  • Page 205 S3F80P5_UM_ REV1.00 INSTRUCTION SET SWAP — Swap Nibbles SWAP dst (0 – 3) ↔ dst (4 – 7) Operation: The contents of the lower four bits and upper four bits of the destination operand are swapped. Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set;...
  • Page 206 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Test Complement Under Mask dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
  • Page 207 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.
  • Page 208 INSTRUCTION SET S3F80P5_UM_ REV1.00 — Wait For Interrupt Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt .
  • Page 209 S3F80P5_UM_ REV1.00 INSTRUCTION SET — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...
  • Page 210 INSTRUCTION SET S3F80P5_UM_ REV1.00 NOTES 6-88...

  • Page 211: Chapter 7 Clock And Power Circuit

    S3F80P5_UM_ REV1.00 CLOCK AND POWER CIRCUITS CLOCK AND POWER CIRCUITS OVERVIEW The clock frequency for the S3F80P5 can be generated by an external crystal or supplied by an external clock source. The clock frequency for the S3F80P5 can range from 1MHz to 8 MHz. The maximum CPU clock frequency, as determined by CLKCON register, is 8 MHz.
  • Page 212 CLOCK AND POWER CIRCUITS S3F80P5_UM_ REV1.00 Figure 7-1. Main Oscillator Circuit (External Crystal or Ceramic Resonator) External Clock Open Pin Figure 7-2. External Clock Circuit...

  • Page 213: Clock Status During Power-Down Modes

    S3F80P5_UM_ REV1.00 CLOCK AND POWER CIRCUITS CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. When stop mode is released, the oscillator starts by a reset operation or by an external interrupt.

  • Page 214: System Clock Control Register (Clkcon)

    CLOCK AND POWER CIRCUITS S3F80P5_UM_ REV1.00 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H, Set1, Bank0. It is read/write addressable and has the following functions: — Oscillator frequency divide-by value The CLKCON.7– .5 and CLKCON.2- .0 Bit are not used in S3F80P5. After a reset, the main oscillator is activated, and the f (the slowest clock speed) is selected as the CPU clock.
  • Page 215 S3F80P5_UM_ REV1.00 CLOCK AND POWER CIRCUITS Figure 7-5. Power Circuit (VDD) Typically, application systems have a resister and two separate capacitors across the power pins. R1 and C1 located as near to the MCU power pins as practical to suppress high-frequency noise. C2 should be a bulk electrolytic capacitor to provide bulk charge storage for the overall system.
  • Page 216 CLOCK AND POWER CIRCUITS S3F80P5_UM_ REV1.00 NOTES...

  • Page 217: Reset

    S3F80P5_UM_ REV1.00 RESET RESET OVERVIEW Resetting the MCU is the function to start processing by generating reset signal using several reset schemes. During reset, most control and status are forced to initial values and the program counter is loaded from the reset vector.
  • Page 218 RESET S3F80P5_UM_ REV1.00 STOP IPOR Watchdog Timer RESET P0&P2.0 (INT0-INT5) (EI)external interrupt enable RESET Contorl Bit '1' STOP RESET Contorl Bit '1' *RESET Control Bit : smart option bit[0]@03FH STOP Figure 8-1. RESET Sources of the S3F80P5 1. The rising edge detection of LVD circuit while rising of VDD passes the level of V When POR circuit detects VDD below V , reset is generated by internal power-on reset.
  • Page 219 S3F80P5_UM_ REV1.00 RESET Falling Edge Back-up Enable/ Detector STOP Mode Disable Rising Edge STOPCON Detector IPOR fosc (WDT) RESET RESET Contorl Bit'1' STOP STOPCON Enabled External Interrupt P0& P2.0 INT0~INT5 Control Block Noise P0&P2.0 Filter (INT0~INT5) SED&R Falling Edge Circuit STOPCON STOP *RESET Control Bit: smart option bit [ 0] @03FH...

  • Page 220: Reset Mechanism

    RESET S3F80P5_UM_ REV1.00 RESET MECHANISM The interlocking work of reset pin and LVD circuit supplies two operating modes: back-up mode input, and system reset input. Back-up mode input automatically creates a chip stop state when the voltage at V is lower than .

  • Page 221: Internal Power-On Reset

    S3F80P5_UM_ REV1.00 RESET INTERNAL POWER-ON RESET The power-on reset circuit is built on the S3F80P5 product. When power is initially applied to the MCU, or when drops below the V , the POR circuit holds the MCU in reset until V has risen above the V level.

  • Page 222: External Interrupt Reset

    RESET S3F80P5_UM_ REV1.00 If "Vreset > VIH", the operating status is in STOP mode, LVD circuit is disabled in the S3F80P5X. WAIT Stop Mode (LVD off) Reset Low (4096x16x1/fosc) Normal Operating Mode (LVD on) Reset pulse generated, Oscillation starts POR detected...

  • Page 223: Stop Error Detection & Recovery

    S3F80P5_UM_ REV1.00 RESET STOP ERROR DETECTION & RECOVERY When RESET Control Bit (smart option bit [0] @ 03FH) is set to ‘0’ and chip is in stop or abnormal state, the falling edge input of P0 generates the reset signal. Refer to following table and figure for more information.

  • Page 224: Power-Down Modes

    RESET S3F80P5_UM_ REV1.00 POWER-DOWN MODES The power down mode of S3F80P5 are described following that: — Idle mode — Back- up mode — Stop mode IDLE MODE Idle mode is invoked by the instruction IDLE (op-code 6FH). In Idle mode, CPU operations are halted while some peripherals remain active.

  • Page 225: Back-Up Mode

    S3F80P5_UM_ REV1.00 RESET BACK-UP MODE For reducing current consumption, S3F80P5 goes into Back-up mode. If a falling level of V is detected by LVD circuit on the point of V , chip goes into the back-up mode. CPU and peripheral operation are stopped, but LVD is enabled.
  • Page 226 RESET S3F80P5_UM_ REV1.00 tWAIT Stop Mode (LVD off) Normal Operating Mode Key-in LVD ON Stop Mode (LVD off) Back-up Mode Normal Operating Mode tWAIT Reset pulse generated, oscillation start Key-in LVD ON Figure 8-8. Timing Diagram for Back-up Mode Input in Stop Mode 8-10...

  • Page 227: Stop Mode

    S3F80P5_UM_ REV1.00 RESET STOP MODE STOP mode is invoked by executing the instruction ‘STOP’, after setting the stop control register (STOPCON). In STOP mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the current consumption can be reduced.

  • Page 228: Sources To Release Stop Mode

    RESET S3F80P5_UM_ REV1.00 SOURCES TO RELEASE STOP MODE Stop mode is released when following sources go active: — System Reset by Internal Power-On Reset (IPOR) — External Interrupt (INT0-INT5) — SED & R circuit Using IPOR to Release STOP Mode Stop mode is released when the system reset signal goes active by internal power-on reset (IPOR).

  • Page 229: Sed&R (Stop Error Detect And Recovery)

    S3F80P5_UM_ REV1.00 RESET SED&R (Stop Error Detect and Recovery) The Stop Error Detect & Recovery circuit is used to release stop mode and prevent abnormal - stop mode that can be occurred by battery bouncing. It executes two functions in related to the internal logic of P0. One is releasing from stop status by switching the level of input port (P0) and the other is keeping the chip from entering stop mode when the chip is in abnormal status.

  • Page 230: System Reset Operation

    RESET S3F80P5_UM_ REV1.00 SYSTEM RESET OPERATION System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal CPU and peripheral modules. This procedure brings the S3F80P5 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance.

  • Page 231: Hardware Reset Values

    S3F80P5_UM_ REV1.00 RESET HARDWARE RESET VALUES Tables 8-2 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: — A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. —...
  • Page 232 RESET S3F80P5_UM_ REV1.00 Table 8-2. Set 1, Bank 0 Register Values After Reset (Continued) Address Bit Values After Reset Register Name Mnemonic Port 1 Control Register (High Byte) P1CONH Port 1 Control Register (Low Byte) P1CONL Reserved Port 2 Control Register (Low Byte) P2CONL Port 2 Pull-up Enable Register P2PUR...
  • Page 233 S3F80P5_UM_ REV1.00 RESET Table 8-3. Set 1, Bank 1 Register Values After Reset Address Bit Values After Reset Register Name Mnemonic LVD Control Register LVDCON – – – – – – – Reserved Reserved Reserved Timer 2 Counter Register (High Byte) T2CNTH Timer 2 Counter Register (Low Byte) T2CNTL...
  • Page 234 RESET S3F80P5_UM_ REV1.00 Table 8-4. Reset Generation According to the Condition of Smart Option Smart option 1st bit @3FH Mode Reset Source Watch Dog Timer Enable Reset Reset IPOR Reset Reset Normal Reset Reset Operating External Interrupt (EI) P0 and P2 External ISR External ISR External Interrupt (DI) P0 and P2...

  • Page 235: Recommendation For Unusued Pins

    S3F80P5_UM_ REV1.00 RESET RECOMMENDATION FOR UNUSUED PINS To reduce overall power consumption, please configure unused pins according to the guideline description Table 8-5. Table 8-5. Guideline for Unused Pins to Reduced Power Consumption Pin Name Recommend Example P0CONH ← # 00H or 0FFH •...

  • Page 236: Summary Table Of Back-Up Mode, Stop Mode, And Reset Status

    RESET S3F80P5_UM_ REV1.00 SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS For more understanding, please see the below description Table 8-6. Table 8-6. Summary of Each Mode Item/Mode Back-up Reset Status Stop STOPCON ← # A5H • • •...

  • Page 237: Overview

    S3F80P5_UM_ REV1.00 I/O PORTS I/O PORTS OVERVIEW The S3F80P5 microcontroller has four bit-programmable I/O ports, P0, P1, P2, P3. Two ports, P0 and P1, are 8- bit ports and P2 is a 1-bit port and P3 is a 2-bit port. This gives a total of 19 I/O pins. Each port is bit-programmable and can be flexibly configured to meet application design requirements.
  • Page 238 I/O PORTS S3F80P5_UM_ REV1.00 Table 9-1. S3F80P5 Port Configuration Overview (24-SOP) Port Configuration Options Port 0 8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable register (P0INT) and pending control register (P0PND);...

  • Page 239: Port Data Registers

    S3F80P5_UM_ REV1.00 I/O PORTS PORT DATA REGISTERS Table 9-4 gives you an overview of the register locations of all four S3F80P5 I/O port data registers. Data registers for ports 0,1 have the general format shown in Figure 9-1. NOTE The data register for port 3, P3, contains 2-bits for P3.0−P3.1, and an additional status bit (P3.7) for carrier signal on/off.

  • Page 240: Pull-Up Resistor Enable Registers

    I/O PORTS S3F80P5_UM_ REV1.00 PULL-UP RESISTOR ENABLE REGISTERS You can assign pull-up resistors to the pin circuits of individual pins in port0 and port1. To do this, you make the appropriate settings to the corresponding pull-up resistor enable registers; P0PUR. These registers are located in set 1, bank 0 at locations E7H, respectively, and are read/write accessible using Register addressing mode.

  • Page 241: Overview

    S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 OVERVIEW The S3F80P5 has two default timers: the 8-bit basic timer and the 8-bit general-purpose timer/counter. The 8-bit timer/counter is called timer 0. BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: —...

  • Page 242: Basic Timer Control Register (Btcon)

    BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watch-dog timer function. It is located in Set 1 and Bank0, addresses D3H, and is read/write addressable using register addressing mode.

  • Page 243: Basic Timer Function Description

    S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watch-dog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than '1010B'. (The '1010B' value disables the watch-dog function.) A reset clears BTCON to '00H', automatically enabling the watch-dog timer function.

  • Page 244: Timer 0 Control Register (T0Con)

    BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 TIMER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to — Select the timer 0 operating mode (interval timer, capture mode, or PWM mode) — Select the timer 0 input clock frequency —...
  • Page 245 S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 Timer 0 Control Register (T0CON) D2H, Set 1, Bank0 , R/W Timer 0 Interrupt Pending Bit: 0 = No interrupt pending Timer 0 Input Clock Selection Bits: 0 = Clear pending bit (when write) 00 = f /4096 1 = Interrupt is pending...

  • Page 246: Timer 0 Function Description

    BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0, Vectors FAH and FCH) The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/ capture interrupt (T0INT). T0OVF is interrupt with level IRQ0 and vector FAH. T0INT also belongs to interrupt level IRQ0, but is assigned the separate vector address, FCH.

  • Page 247: Pulse Width Modulation Mode

    S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register.

  • Page 248: Capture Mode

    BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 Capture Mode In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter value into the T0 data register. You can select rising or falling edges to trigger this operation. Timer 0 also gives you capture input source: the signal edge at the T0CAP pin.
  • Page 249 S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 Bit 1 RESET or STOP Bits 3, 2 Basic Timer Control Register Data Bus (Write'1010xxxxB ' to disable .) Clear 1/16384 1/4096 8-Bit Up Counter RESET (BTCNT , Read-Only) 1/1024 1/128 When BTCNT .4 is set after releasing from RESET or STOP mode , CPU clock starts .
  • Page 250 BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 PROGRAMMING TIP — Configuring the Basic Timer This example shows how to configure the basic timer to sample specifications: 0100H RESET ; Disable all interrupts BTCON,#0AAH ; Disable the watchdog timer CLKCON,#18H ; Non-divided clock ;...
  • Page 251 S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 PROGRAMMING TIP — Programming Timer 0 This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows: —...
  • Page 252 BASIC TIMER and TIMER 0 S3F80P5_UM_ REV1.00 PROGRAMMING TIP — Programming Timer 0 (Continued) ; 50 × 4 = 200 ms R0,#32H ULT,NO_200MS_SET BITS R1.2 ; Bit setting (61.2H) NO_200MS_SET: T0CON,#42H ; Clear pending bit ; Restore register pointer 0 value T0OVER IRET ;...

  • Page 253: Overview

    S3F80P5_UM_ REV1.00 TIMER 1 TIMER 1 OVERVIEW The S3F80P5 microcontroller has a 16-bit timer/counter called Timer 1 (T1). For universal remote controller applications, Timer 1 can be used to generate the envelope pattern for the remote controller signal. Timer 1 has the following components: —...

  • Page 254: Timer 1 Overflow Interrupt

    TIMER 1 S3F80P5_UM_ REV1.00 TIMER 1 OVERFLOW INTERRUPT Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the 16-bit up counter. When you set the Timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt is generated each time the 16-bit up counter reaches ‘FFFFH’.

  • Page 255: Timer 1 Match Interrupt

    S3F80P5_UM_ REV1.00 TIMER 1 TIMER 1 MATCH INTERRUPT Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value matches the value that is written to the Timer 1 reference data registers, T1DATAH and T1DATAL. When a match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up counting resumes from ‘00H’.
  • Page 256 TIMER 1 S3F80P5_UM_ REV1.00 T1CON.2 T1CON. 7-.6 IRQ1 CAOF (T-F/F) Clear T1CON.3 16-Bit Up-Counter (Read-Only) Match (note) T1CON.1 16-Bit Compatator T1CON.5-.4 T1CON.0 IRQ1 Timer 1 High/Low Buffer Register T1CON.3 Match Signal T1OVF Timer 1 Data High/Low Register Data Bus NOTE: Match signal is occurrd only in interval mode.

  • Page 257: Timer 1 Control Register (T1Con)

    S3F80P5_UM_ REV1.00 TIMER 1 TIMER 1 CONTROL REGISTER (T1CON) The Timer 1 control register, T1CON, is located in Set 1, FAH, Bank0 and is read/write addressable. T1CON contains control settings for the following T1 functions: — Timer 1 input clock selection —...
  • Page 258 TIMER 1 S3F80P5_UM_ REV1.00 Timer1 Counter High-byte Register (T1CNTH) F6H, Set 1, Bank 0, R Reset Value: 00H Timer 1 Counter Low-byte Register (T1CNTL) F7H, Set 1, Bank 0, R Reset Value: 00H Timer 1 Data High-byte Register (T1DATAH) F8H, Set 1, Bank 0, R/W Reset Value: FFH Timer 1 Data Low-byte Register (T1DATAL) F9H, Set 1, Bank 0, R/W...

  • Page 259: Overview

    S3F80P5_UM_ REV1.00 COUNTER A COUNTER A OVERVIEW The S3F80P5 microcontroller has one 8-bit counter called counter A. Counter A, which can be used to generate the carrier frequency, has the following components (See Figure 12-1): — Counter A control register, CACON —...
  • Page 260 COUNTER A S3F80P5_UM_ REV1.00 CACON.6-.7 DIV 1 DIV 2 CACON.0 To Other Block 8-Bit Down Counter (CAOF) DIV 4 (P3.1/REM) DIV 8 Repeat CACON.3 Control Interrupt IRQ2 INT. GEN. Control (CAINT) Counter A Data Low Byte Register CACON.2 CACON.4-.5 Counter A Data High Byte Register Data Bus NOTE:...

  • Page 261: Counter A Control Register (Cacon)

    S3F80P5_UM_ REV1.00 COUNTER A COUNTER A CONTROL REGISTER (CACON) The counter A control register, CACON, is located in F3H, Set 1, Bank 0, and is read/write addressable. CACON contains control settings for the following functions (See Figure 12-2): — Counter A clock source selection —...

  • Page 262: Counter A Pulse Width Calculations

    COUNTER A S3F80P5_UM_ REV1.00 COUNTER A PULSE WIDTH CALCULATIONS HIGH To generate the above repeated waveform consisted of low period time, t , and high period time, t HIGH. When CAOF = 0, = (CADATAL + 2) × 1/Fx. 0H < CADATAL < 100H, where Fx = the selected clock. = (CADATAH + 2) ×...
  • Page 263 S3F80P5_UM_ REV1.00 COUNTER A 100H 200H Counter A Clock CAOF = '0' CADATAL = 01-FFH High CADATAH = 00H CAOF = '0' CADATAL = 00H CADATAH = 01-FFH CAOF = '0' CADATAL = 00H CADATAH = 00H CAOF = '1' High CADATAL = 00H CADATAH = 00H...
  • Page 264 COUNTER A S3F80P5_UM_ REV1.00 PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.1 This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are: 8.795 us 17.59 us 37.9 kHz 1/3 duty...
  • Page 265 S3F80P5_UM_ REV1.00 COUNTER A PROGRAMMING TIP — To generate a one-pulse signal through P3.1 This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 40 μs width pulse. The program parameters are: 40 us —...
  • Page 266 COUNTER A S3F80P5_UM_ REV1.00 NOTES 12-8...

  • Page 267: Overview

    S3F80P5_UM_ REV1.00 TIMER 2 TIMER 2 OVERVIEW The S3F80P5 microcontroller has a 16-bit timer/counter called Timer 2 (T2). For universal remote controller applications, timer 2 can be used to generate the envelope pattern for the remote controller signal. Timer 2 has the following components: •...

  • Page 268: Timer 2 Overflow Interrupt

    TIMER 2 S3F80P5_UM_ REV1.00 TIMER 2 OVERFLOW INTERRUPT Timer 2 can be programmed to generate an overflow interrupt (IRQ3, F0H) whenever an overflow occurs in the 16-bit up counter. When you set the timer 2 overflow interrupt enable bit, T2CON.2, to “1”, the overflow interrupt is generated each time the 16-bit up counter reaches ‘FFFFH’.

  • Page 269: Timer 2 Match Interrupt

    S3F80P5_UM_ REV1.00 TIMER 2 TIMER 2 MATCH INTERRUPT Timer 2 can also be used to generate a match interrupt (IRQ3, vector F2H) whenever the 16-bit counter value matches the value that is written to the timer 2 reference data registers, T2DATAH and T2DATAL. When a match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up counting resumes from ‘00H’.
  • Page 270 TIMER 2 S3F80P5_UM_ REV1.00 T2CON.2 T2CON. 7-.6 IRQ3 CAOF (T-F/F) Clear T2CON.3 16-Bit Up-Counter (Read-Only) Match (note) T2CON.1 16-Bit Compatator T2CON.5-.4 T1CON.0 IRQ3 Timer 2 High/Low Buffer Register T1CON.3 Match Signal T2OVF Timer 2 Data High/Low Register Data Bus NOTE: Match signal is occurrd only in interval mode.

  • Page 271: Timer 2 Control Register (T2Con)

    S3F80P5_UM_ REV1.00 TIMER 2 TIMER 2 CONTROL REGISTER (T2CON) The timer 2 control register, T2CON, is located in address E8H, Bank1, Set 1 and is read/write addressable. T2CON contains control settings for the following T2 functions: • Timer 2 input clock selection •...
  • Page 272 TIMER 2 S3F80P5_UM_ REV1.00 Timer2 Counter High-Byte Register (T2CNTH) E4H , Set 1, Bank 1, Read-only Reset Value: 00H Timer 2 Counter Low-Byte Register (T2CNTL) E5H , Set 1, Bank 1, Read-only Reset Value: 00H Timer 2 Data High-Byte Register (T2DATAH) E6H , Set 1, Bank 1, R/W Reset Value: FFH Timer 2 Data Low-Byte Register (T2DATAL)

  • Page 273: Flash Rom Configuration

    S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F80P5 has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by instruction ‘LDC’. This is a sector erasable and a byte programmable flash. User can program the data in a flash memory area any time you want.

  • Page 274: User Program Mode

    EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 User Program Mode This mode supports sector erase, byte programming, byte read and one protection mode (Hard Lock Protection). The S3F80P5 has the internal pumping circuit to generate high voltage. Therefore, 12.5V into Vpp (TEST) pin is not needed.

  • Page 275: Smart Option

    S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE SMART OPTION Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80P5 only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH).

  • Page 276: Isp Reset Vector And Isp Sector Size

    EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 NOTES 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless. 2.

  • Page 277: Flash Memory Control Registers (User Program Mode)

    S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE) FLASH MEMORY CONTROL REGISTER (FMCON) FMCON register is available only in user program mode to select the flash memory operation mode; sector erase, byte programming, and to make the flash memory into a hard lock protection. Flash Memory Control Register (FMCON ) EFH , Set 1 , Bank 1 , R/W...

  • Page 278: Flash Memory Sector Address Registers

    EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers for the erase or programming flash memory. The FMSECL (Flash Memory Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory Address Sector Register High Byte) indicates the high byte of sector address.

  • Page 279: Sector Erase

    S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE SECTOR ERASE User can erase a flash memory partially by using sector erase function only in user program mode. The only unit of flash memory to be erased in the user program mode is a sector. The program memory of S3F80P5, 18Kbytes flash memory, is divided into 144 sectors.

  • Page 280: The Sector Erase Procedure In User Program Mode

    EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”. 2. Set Flash Memory Sector Address Register (FMSECH and FMSECL). 3. Set Flash Memory Control Register (FMCON) to “10100001B”. 4.
  • Page 281 S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING TIP — Sector Erase Case1. Erase one sector • • ERASE_ONESECTOR: FMUSR,#0A5H ; User program mode enable FMSECH,#40H ; Set sector address 4000H,sector 128, FMSECL,#00H ; among sector 0~511 FMCON,#10100001B ; Select erase mode enable & Start sector erase ERASE_STOP: FMUSR,#00H ;...
  • Page 282 EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 SECTOR_ERASE: R12,SecNumH R14,SecNumL MULT RR12,#80H ; Calculation the base address of a target sector MULT RR14,#80H ; The size of one sector is 128-bytes R13,R14 ; BTJRF FLAGS.7,NOCARRY ; INC NOCARRY: R10,R13 R11,R15 ERASE_START: FMUSR,#0A5H ;...

  • Page 283: Programming

    S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING A flash memory is programmed in one-byte unit after sector erase. The write operation of programming starts by ‘LDC’ instruction. The program procedure in user program mode 1. Must erase target sectors before programming. 2.
  • Page 284 EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 Start ; Select Bank1 FMSECH High Address of Sector ; Set Secotr Base Address FMSECL Low Address of Sector R(n) High Address to Write R(n+1) Low Address to Write ; Set Address and Data R(data) 8-bit Data FMUSR...
  • Page 285 S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE Start ; Select Bank1 ; Set Secotr Base Address FMSECH High Address of Sector FMSECL Low Address of Sector R(n) High Address to Write ; Set Address and Data R(n+1) Low Address to Write R(data) 8-bit Data FMUSR...
  • Page 286 EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 PROGRAMMING TIP — Programming Case1. 1-byte programming • • WR_BYTE: ; Write data “AAH” to destination address 4010H FMUSR,#0A5H ; User program mode enable FMCON,#01010000B ; Selection programming mode FMSECH, #40H ; Set the base address of sector (4000H) FMSECL, #00H R9,#0AAH ;...
  • Page 287 S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE Case3. Programming to the flash memory space located in other sectors • • WR_INSECTOR2: R0,#40H R1,#40H FMUSR,#0A5H ; User program mode enable LD FMCON,#01010000B ; Selection programming mode and Start programming LD FMSECH,#01H ; Set the base address of sector located in target address to write data FMSECL,#00H ;...

  • Page 288: Reading

    EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 READING The read operation starts by ‘LDC’ instruction. The program procedure in user program mode 1. Load a flash memory upper address into upper register of pair working register. 2. Load a flash memory lower address into lower register of pair working register. 3.

  • Page 289: Hard Lock Protection

    S3F80P5_UM_ REV1.00 EMBEDDED FLASH MEMORY INTERFACE HARD LOCK PROTECTION User can set Hard Lock Protection by writing ‘0110B’ in FMCON7-4. This function prevents the changes of data in a flash memory area. If this function is enabled, the user cannot write or erase the data in a flash memory area. This protection can be released by the chip erase execution in the tool program mode.
  • Page 290 EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1.00 NOTES 14-18...
  • Page 291 S3F80P5_UM_ REV1.00 LOW VOLTAGE DETECTOR LOW VOLTAGE DETECTOR OVERVIEW The S3F80P5 micro-controller has a built-in Low Voltage Detector (LVD) circuit, which allows LVD and LVD_FLAG detection of power voltage. The S3F80P5 has two options in LVD and LVD_FLAG voltage level according to the operating frequency to be set by smart option (Refer to the page 2-4).
  • Page 292 LOW VOLTAGE DETECTOR S3F80P5_UM_ REV1.00 NOTES 1. A term of LVD is a symbol of parameter that means ‘Low Level Detect Voltage for Back-Up Mode’. 2. A term of LVD_FLAG is a symbol of parameter that means ‘Low Level Detect Voltage for Flag Indicator’.

  • Page 293: Low Voltage Detector Control Register (Lvdcon)

    S3F80P5_UM_ REV1.00 LOW VOLTAGE DETECTOR LOW VOLTAGE DETECTOR CONTROL REGISTER (LVDCON) LVDCON.0 is used flag bit to indicate low battery in IR application or others. When LVD circuit detects LVD_FLAG, LVDCON.0 flag bit is set automatically. The reset value of LVDCON is #00H. Low Voltage Detect Control Register (LVDCON ) E 0 H , Set 1, Bank 1, R /W...

  • Page 294: Electrical Data

    S3F80P5_UM_ REV1.00 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, S3F80P5 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: • Absolute Maximum Ratings • D.C. Electrical Characteristics • Characteristics of Low Voltage Detect Circuit •...
  • Page 295 ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-1. Absolute Maximum Ratings = 25 °C) Parameter Symbol Conditions Rating *TBD Unit − − 0.3 to + 3.8 Supply Voltage − − 0.3 to V Input Voltage + 0.3 − 0.3 to V Output Voltage All output pins + 0.3 −...
  • Page 296 S3F80P5_UM_ REV1.00 ELECTRICAL DATA Table 16-2. D.C. Electrical Characteristics (Continued) = -25 °C to + 85 °C, V = 1.60 V to 3.6 V) Parameter Symbol Conditions Unit − = 1.70 V, I = 8mA Output Low Voltage Port 3.1 only = 1.70 V, I = 5mA P3.0 and P2.0...
  • Page 297 ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-2. D.C. Electrical Characteristics (Continued) = -25 °C to + 85 °C, V = 1.60 V to 3.6 V) Parameter Symbol Conditions Unit − (note2) Supply Current Operating Mode = 3.6 V (note1) 8 MHz crystal −...
  • Page 298 S3F80P5_UM_ REV1.00 ELECTRICAL DATA NOTE: The voltage gaps (LVD_GAPn (n=1~4)) between LVD and LVD FLAGn(n=1~4) have ± 80mV distribution. LVD and LVD FLAGn(n=1~4) are not overlapped. The variation of LVD FLAGn(n=1~4) and LVD always is shifted in same direction. That is, if one chip has positive tolerance (e.g. +50mV) in LVD FLAG, LVD has positive tolerance. Symbol Unit LVD_GAP1...
  • Page 299 ELECTRICAL DATA S3F80P5_UM_ REV1.00 Idle Mode (Basic Timer Active) Stop Mode Data Retention Mode Normal Operating Mode DDDR Execution of STOP Instrction EXT INT 0.8V 0.2V WAIT Figure 16-1. Stop Mode Release Timing When Initiated by an External Interrupt 16-6...
  • Page 300 S3F80P5_UM_ REV1.00 ELECTRICAL DATA Reset Oscillation Stabilization Time Occur Stop Mode Normal Operating Mode Back-up Mode DDDR WAIT Execution of STOP Instrction Data Retention Time NOTE: is the same as 4096 x 16 x 1/f WAIT Figure 16-2. Stop Mode Release Timing When Initiated by a LVD Table 16-6.
  • Page 301 ELECTRICAL DATA S3F80P5_UM_ REV1.00 INTL INTH 0.8 V 0.8 V 0.2 V 0.2 V NOTE: The unit t means one CPU clock period. Figure 16-3. Input Timing for External Interrupts (Port 0 and Port 2) 16-8...
  • Page 302 S3F80P5_UM_ REV1.00 ELECTRICAL DATA Table 16-8. Oscillation Characteristics = -25 °C to + 85 °C) Oscillator Clock Circuit Conditions Unit − Crystal CPU clock oscillation frequency − Ceramic CPU clock oscillation frequency − input frequency External Clock External Clock Open Pin 16-9...
  • Page 303 ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-9. Oscillation Stabilization Time = -25 °C to + 85 °C, V = 3.6 V) Oscillator Test Condition Unit − − > 1 MHz Main crystal − − Oscillation stabilization occurs when V is equal Main ceramic to the minimum oscillator voltage range.
  • Page 304 S3F80P5_UM_ REV1.00 ELECTRICAL DATA Minimun Instruction (Main Oscillator Frequency) Clock 2 MHz 8 MHz 1.5MHz 6 MHz 4 MHz 1MHz 500 kHz 2 MHz 250 kHz 1 MHz 400 kHz 1kHz Supply Voltage (V) Minimun Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16) A: 1.65 V, 8 MHz Figure 16-4.
  • Page 305 ELECTRICAL DATA S3F80P5_UM_ REV1.00 Table 16-11. ESD Characteristics Parameter Symbol Conditions Unit − − Electrostatic discharge 2000 − − − − NOTE: If on board programming is needed, it is recommended that add a 0.1uF capacitor between TEST pin and VSS for better noise immunity;...

  • Page 306: Mechanical Data

    S3F80P5_UM_ REV1.00 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3F80P5 micro-controller is currently available in a 24-pin SOP and SDIP package. 24-SOP-375 + 0.10 0.15 - 0.05 15.74 MAX ± 0.20 15.34 0.10 MAX 1.27 (0.69) + 0.10 0.38 - 0.05 NOTE: Dimensions are in millimeters.
  • Page 307 MECHANICAL DATA S3F80P5_UM_ REV1.00 0-15 24-SDIP-300 23.35 MAX ± 0.20 22.95 ± 0.10 0.46 1.778 ± 0.10 (1.70) 0.89 NOTE: Dimensions are in millimeters. Figure 17-2. 24-Pin SDIP Package Mechanical Data 17-2...
  • Page 308 S3F80P5_UM_ REV1.00 S3F80P5 FLASH MCU S3F80P5 FLASH MCU OVERVIEW The S3F80P5 single-chip CMOS microcontroller is the Flash MCU. It has an on-chip Flash MCU ROM. The Flash ROM is accessed by serial data format. NOTE This chapter is about the Tool Program Mode of Flash MCU. If you want to know t he User Program Mode, apter 14.
  • Page 309 S3F80P5 FLASH MCU S3F80P5_UM_ REV1.00 P2.0/INT5 P3.1/REM/T0CK Xout P3.0/T0PWM/T0CAP/T1CAP/T2CAP TEST S3C80P5 P1.7 SDAT/P0.0/INT0 P1.6 SCLK/P0.1/INT1 P1.5 nRESET/P0.2/INT2 24-SOP/SDIP P1.4 P0.3/INT3 (TOP VIEW) P1.3 P0.4/INT4 P1.2 P0.5/INT4 P1.1 P0.6/INT4 P1.0 P0.7/INT4 Figure 18-1. Pin Assignment Diagram (24-Pin SOP/SDIP Package) 18-2...
  • Page 310 S3F80P5_UM_ REV1.00 S3F80P5 FLASH MCU Table 18-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin Name Pin No. Function P0.0 SDAT Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port.

  • Page 311: Operating Mode Characteristics

    S3F80P5 FLASH MCU S3F80P5_UM_ REV1.00 OPERATING MODE CHARACTERISTICS When 3.3 V is supplied to the TEST pin of the S3F80P5, the Flash ROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 22-2 below.

  • Page 312: Target Boards

    DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supporting software. For a host system, any standard computer that employs Win95/98/2000/XP as its operating system can be used. A sophisticated debugging tool is provided both in hardware and software: the powerful in-circuit emulator, OPENice-i500 and SK-1200, for the S3C7-, S3C9-, and S3C8- microcontroller families.
  • Page 313 DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 [Development System Configuration] IBM-PC AT or Compatible Emulator [ SK-1200(RS-232,USB) or RS-232C / USB OPENIce I-500(RS-232) ] Target OTP/MTP Writer Block Application System RAM Break/Display Block Probe Adapter Trace/Timer Block TB80PB SAM8 Base Block Target Board Power Supply Block Chip Figure 19-1.

  • Page 314: Tb80Pb Target Board

    S3F80P5_UM_ REV1.00 ELECTRICAL DATA TB80PB TARGET BOARD The TB80PB target board can be used for development of S3F80P5. The TB80PB target board is operated as target CPU with Emulator (SK-1200, OPENIce I-500) TB80PB Rev1 To User _Vcc nRESET IDLE STOP 74HC11 In-Circuit Emulator RESET...
  • Page 315 DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 Table 19-1. Setting of the Jumper in TB80PB Description 1-2 Connection 2-3 Connection Default Setting Target board power source Use JP7(VCC) NOT connected Join 1-2 Target board mode selection H: Main-Mode L: EVA-Mode Join 2-3 Operation Mode H: User Mode L: Test-Mode Join 1-2...
  • Page 316 S3F80P5_UM_ REV1.00 ELECTRICAL DATA – STOP LED This LED is ON when the evaluation chip (S3E80PB) is in stop mode. 19-5...
  • Page 317 DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 P2.3/INT8 P2.2/INT7 P2.4/INT9/CIN0 P2.1/INT6 P3.0/T0PWM/T0CAP P2.0/INT5 P3.1/REM P4.0 P4.1 P4.2 P4.3 P0.7/INT4 TEST P0.6/INT4 P2.5/INT9/CIN1 P0.5/INT4 P2.6/INT9/CIN2 P0.4/INT4 RESET P0.3/INT3 P3.4 P0.2/INT2 P3.5 P0.1/INT1/SCLK P2.7/INT9/CIN3 P0.0/INT0/SDAT P1.0 P4.4 P3.2/T0CK P4.5 P3.3/T1CAP/T2CAP P4.6 P4.7 P1.7 P1.1 P1.6 P1.2 P1.5 P1.3...

  • Page 318: Third Parties For Development Tools

    SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In- circuit emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with an OTP/MTP programmer.

  • Page 319: Otp/Mtp Programmer (Writer)

    • URL: programmer http://www.seminix.com (Read, Program, Verify, Blank, Protection..) • Fast programming speed (4Kbyte/sec) • Support all of SAMSUNG OTP/MTP/FLASH MCU devices • Low-cost • NOR Flash memory (SST,Samsung…) • NAND Flash memory (SLC) • New devices will be supported just by adding device files or upgrading the software.
  • Page 320 • PC-based menu-drive software for simple operation • Very fast program and verify time ( OTP:2Kbytes per second, MTP:10Kbytes per second) • Support Samsung standard Hex or Intel Hex format • Driver software run under various O/S (Windows 95/98/2000/XP) • Full function regarding OTP/MTP programmer (Read, Program, Verify, Blank, Protection..)
  • Page 321 DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 NOTES 19-10...

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