Samsung S3F84B8 Manuals

Table of Contents

• 18

  Overview of S3F84B8 Microcontroller
• 19

  Key Features of S3F84B8
• 22

  Block Diagram of S3F84B8
• 23

  Pin Assignments
• 24

  Pin Descriptions
• 25

  Table 1-2 Pin Descriptions Used to Read/Write the Flash ROM
• 26

  Pin Circuits
• 27

  Figure 1-5 Pin Circuit Type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7)
• 31

  Address Spaces
• 32

  Internal Program Memory (ROM)
• 33

  Smart Option
• 34

  Register Architecture
• 35

  Figure 2-3 Internal Register File Organization in S3F84B8
• 36

  Register Page Pointer (PP)
• 37

  Register Set 1
• 38

  Prime Register Space
• 39

  Working Registers
• 40

  Using the Register Points (RP)
• 41

  Figure 2-8 Non-Contiguous 16 Byte Working Register Block
• 42

  Register Addressing
• 44

  Common Working Register Area (C0H–CFH)
• 45

  Bit Working Register Addressing
• 46

  Figure 2-13 4-Bit Working Register Addressing Example
• 47

  Bit Working Register Addressing
• 48

  Figure 2-15 8-Bit Working Register Addressing Example
• 49

  System and User Stack
• 51

  Addressing Modes
• 52

  Register (R) Addressing Mode
• 53

  Indirect Register (IR) Addressing Mode
• 54

  Indirect Register (IR) Addressing Mode (Continued)
• 55

  Indirect Register (IR) Addressing Mode (Continued)
• 56

  Indirect Register (IR) Addressing Mode (Concluded)
• 57

  Indexed (X) Addressing Mode
• 58

  Indexed (X) Addressing Mode (Continued)
• 59

  Indexed (X) Addressing Mode (Concluded)
• 60

  Direct Address (DA) Mode
• 61

  Direct Address (DA) Mode (Continued)
• 62

  Indirect Address (IA) Mode
• 63

  Relative Address (RA) Mode
• 64

  Immediate Mode (IM)
• 65

  Control Registers
• 69

  ADCON — A/D Converter Control Register: FAH, BANK0
• 70

  AMTDATA — Anti-Mis-Trigger Data Register: F6H, BANK0
• 71

  BUZCON — BUZ Control Register: F7H, BANK0
• 72

  CLKCON — Clock Control Register: D4H, BANK0
• 73

  CMP0CON — Comparator0 Control Register: EAH, BANK0
• 74

  CMP1CON — Comparator1 Control Register: EBH, BANK0
• 75

  CMP2CON — Comparator1 Control Register: ECH, BANK0
• 76

  CMP3CON — Comparator1 Control Register: EDH, BANK0
• 77

  CMPINT — Comparator Interrupt Mode Control Register: EEH, BANK0
• 78

  FLAGS — System Flags Register: D5H, BANK0
• 79

  FMCON — Flash Memory Control Register: F5H, BANK1
• 80

  FMSECL — Flash Memory Sector Address Register (Low Byte): F8H, BANK1
• 81

  IMR — Interrupt Mask Register: DDH, BANK0
• 82

  IPH — Instruction Pointer (High Byte): DAH, BANK0
• 83

  IPR — Interrupt Priority Register: FFH, BANK0
• 84

  IRQ — Interrupt Request Register: DCH, BANK0
• 85

  OPACON — OP AMP Control Register: E0H, BANK1
• 86

  P0CONH — Port 0 Control Register (High Byte): E4H, Bank0
• 87

  P0CONL — Port 0 Control Register (Low Byte): E5H, BANK0
• 88

  P0INT — Port 0 Interrupt Control Register: E3H, BANK0
• 89

  P0PND — Port 0 Interrupt Pending Register: E6H, BANK0
• 90

  P1CON — Port 1 Control Register: E7H, BANK0
• 91

  P2CONH — Port 2 Control Register (High Byte): E8H, BANK0
• 92

  P2CONL — Port 2 Control Register (Low Byte): E9H, BANK0
• 93

  PWMCON — PWM Control Register: EFH, BANK0
• 94

  PWMCCON — PWM CMP Control Register: F0H, BANK0
• 95

  PWMDL — Comparator0 Output Delay Register: F5H, Bank0
• 96

  RESETID — Reset Source Indicating Register: F2H, BANK1
• 97

  RP0 — Register Pointer 0: D6H, BANK0
• 98

  SPL — Stack Pointer: D9H, BANK0
• 99

  SYM — System Mode Register: DEH, BANK0
• 100

  TACON — Timer a Control Register: E1H, BANK1
• 101

  TAPS — TA Pre-Scalar Register: E2H, BANK1
• 102

  TCCON — Timer C Control Register: E5H, BANK1
• 103

  TCPS — TC Pre-Scalar Register: E6H, BANK1
• 104

  TDCON — Timer D Control Register: E9H, BANK1
• 105

  TDPS — TD Pre-Scalar Register: EAH, BANK1
• 106

  Interrupt Structure
• 107

  Interrupt Types
• 108

  S3F84B8 Interrupt Structure
• 109

  Interrupt Vector Addresses
• 110

  System-Level Interrupt Control Registers
• 111

  Interrupt Processing Control Points
• 112

  Peripheral Interrupt Control Registers
• 113

  System Mode Register (SYM)
• 114

  Interrupt Mask Register (IMR)
• 115

  Interrupt Priority Register (IPR)
• 117

  Interrupt Request Register (IRQ)
• 118

  Interrupt Pending Function Types
• 119

  Interrupt Source Polling Sequence
• 120

  Generating Interrupt Vector Addresses
• 121

  Instruction Pointer (IP)
• 122

  Procedure for Initiating Fast Interrupts
• 123

  Instruction Set
• 127

  Flags Register (FLAGS)
• 128

  Flag Descriptions
• 129

  Instruction Set Notation
• 130

  Table 6-4 Instruction Notation Conventions
• 131

  Table 6-5 Opcode Quick Reference
• 133

  Condition Codes
• 134

  Instruction Descriptions
• 135

  ADC — Add with Carry
• 136

  ADD — Add
• 137

  AND — Logical and
• 138

  BAND — Bit and
• 139

  BCP — Bit Compare
• 140

  BITC — Bit Complement
• 141

  BITR — Bit Reset
• 142

  BITS — Bit Set
• 143

  BOR — Bit or
• 144

  BTJRF — Bit Test, Jump Relative On False
• 145

  BTJRT — Bit Test, Jump Relative On True
• 146

  BXOR — Bit XOR
• 147

  CALL — Call Procedure
• 148

  CCF — Complement Carry Flag
• 149

  CLR — Clear
• 150

  COM — Complement
• 151

  CP — Compare
• 152

  CPIJE — Compare, Increment, and Jump On Equal
• 153

  CPIJNE — Compare, Increment, and Jump On Non-Equal
• 154

  DA — Decimal Adjust
• 155

  DA — Decimal Adjust (Continued)
• 156

  DEC — Decrement
• 157

  DECW — Decrement Word
• 158

  DI — Disable Interrupts
• 159

  DIV — Divide (Unsigned)
• 160

  DJNZ — Decrement and Jump if Non-Zero
• 161

  EI — Enable Interrupts
• 162

  ENTER — Enter
• 163

  Figure 6-3 Example of the Usage of EXIT Statement
• 164

  IDLE — Idle Operation
• 165

  INC — Increment
• 166

  INCW — Increment Word
• 167

  IRET — Interrupt Return
• 168

  JP — Jump
• 169

  JR — Jump Relative
• 170

  LD — Load
• 171

  LD — Load (Continued)
• 172

  LDB — Load Bit
• 173

  LDC/LDE — Load Memory
• 174

  LDC/LDE — Load Memory (Continued)
• 175

  LDCD/LDED — Load Memory and Decrement
• 176

  LDCI/LDEI — Load Memory and Increment
• 177

  LDCPD/LDEPD — Load Memory with Pre-Decrement
• 178

  LDCPI/LDEPI — Load Memory with Pre-Increment
• 179

  LDW — Load Word
• 180

  MULT — Multiply (Unsigned)
• 181

  NEXT — Next
• 182

  NOP — No Operation
• 183

  OR — Logical or
• 184

  POP — Pop From Stack
• 185

  POPUD — Pop User Stack (Decrementing)
• 186

  POPUI — Pop User Stack (Incrementing)
• 187

  PUSH — Push to Stack
• 188

  PUSHUD — Push User Stack (Decrementing)
• 189

  PUSHUI — Push User Stack (Incrementing)
• 190

  RCF — Reset Carry Flag
• 191

  RET — Return
• 192

  RL — Rotate Left
• 193

  RLC — Rotate Left Through Carry
• 194

  RR — Rotate Right
• 195

  RRC — Rotate Right Through Carry
• 196

  SB0 — Select Bank 0
• 197

  SBC — Subtract with Carry
• 198

  SCF — Set Carry Flag
• 199

  SRA — Shift Right Arithmetic
• 200

  RP/SRP0/SRP1 — Set Register Pointer
• 201

  STOP — Stop Operation
• 202

  SUB — Subtract
• 203

  SWAP — Swap Nibbles
• 204

  TCM — Test Complement Under Mask
• 205

  TM — Test Under Mask
• 206

  WFI — Wait for Interrupt
• 207

  XOR — Logical Exclusive or
• 208

  Clock Circuit
• 209

  Clock Status During Power-Down Modes
• 211

  Reset and Power-Down
• 213

  MCU Initialization Sequence
• 214

  Power-Down Modes
• 215

  Idle Mode
• 216

  Hardware Reset Values
• 219

  I/O Port
• 220

  Port 0
• 221

  Figure 9-1 Port 0 Control Register High Byte (P0CONH)
• 222

  Figure 9-2 Port 0 Control Register Low Byte (P0CONL)
• 223

  Figure 9-3 Port 0 Interrupt Control Register (P0INT)
• 224

  Figure 9-4 Port 0 Interrupt Pending Register (P0PND)
• 225

  Port 1
• 227

  Port 2
• 228

  Figure 9-6 Port 2 High-Byte Control Register (P2CONH)
• 229

  Figure 9-7 Port 2 Low-Byte Control Register (P2CONL)
• 230

  Basic Timer
• 231

  Basic Timer Control Register (BTCON)
• 232

  Basic Timer Function Description
• 233

  Figure 10-2 Oscillation Stabilization Time On RESET
• 234

  Figure 10-3 Oscillation Stabilization Time On STOP Mode Release
• 236

  Bit Timer a
• 237

  Functional Description
• 238

  Timer a Control Register (TACON)
• 241

  Block Diagram of Timer a
• 242

  Timer
• 243

  Functional Description of One 16-Bit Timer Mode (Timer 0)
• 245

  Block Diagram of Timer 0
• 246

  Two 8-Bit Timers Mode (Timer C and D)
• 248

  Figure 12-5 Timer C Prescaler Register (TCPS)
• 250

  Functional Description of Two 8-Bit Timers Mode (Timer C and D)
• 251

  Figure 12-8 Timers C and D Function Block Diagram
• 252

  Pulse Width Modulation Mode (Timer D)
• 253

  A/D Converter
• 254

  Using A/D Pins for Standard Digital Input
• 255

  Internal Reference Voltage Levels
• 257

  Conversion Timing
• 259

  Comparator
• 260

  Figure 14-2 CMP Interrupt Mode Control Register (CMPINT)
• 262

  Comparator 1/2/3
• 264

  Figure 14-7 CMP Interrupt Mode Control Register (CMPINT)
• 266

  Operational Amplifier
• 267

  OPAMP Control Register
• 268

  Reference Circuit
• 269

  Bit Ih-Pwm
• 270

  Functional Description of 10-Bit IH-PWM
• 271

  PWM Functional Description
• 272

  PWM Control Register (PWMCON)
• 273

  PWM CMP Linkage Control Register (PWMCCON)
• 274

  Block Diagram of PWM Module
• 275

  Figure 16-6 Example of the Cooperation of PWM and Comparator 0_Delay Trigger
• 277

  Programmable Buzzer
• 278

  BUZ Frequency Table (@4Mhz)
• 280

  Flash Mcu Rom
• 282

  Embedded Flash Memory Interface
• 283

  User Program Mode
• 284

  Flash Memory Control Registers (User Program Mode)
• 285

  Flash Memory Sector Address Registers
• 286

  Sector Erase
• 287

  Figure 19-7 Sector Erase Flowchart in User Program Mode
• 289

  Programming
• 290

  Figure 19-8 Byte Program Flowchart in a User Program Mode
• 291

  Figure 19-9 Program Flowchart in a User Program Mode
• 295

  Reading
• 296

  Hard Lock Protection
• 297

  Low Voltage Reset
• 299

  Electrical Data
• 300

  Table 21-1 Absolute Maximum Ratings
• 305

  Figure 21-2 Operating Voltage Range @ External Clock
• 306

  Figure 21-4 Stop Mode Release Timing When Initiated By a RESET
• 307

  Table 21-7 A/D Converter Electrical Characteristics
• 308

  Table 21-8 OP AMP Electrical Characteristics
• 309

  Table 21-11 Flash Memory AC Electrical Characteristics
• 310

  Figure 21-6 Circuit Diagram to Improve the EFT Characteristics
• 311

  Development Tools
• 312

  Development System Configuration
• 313

  TB84B8 Target Board
• 317

  Figure 22-5 S3F84B8 Probe Adapter for 20-DIP Package
• 318

  Third Parties for Development Tools
• 319

  OTP/MTP Programmer (Writer)
• 321

  Mechanical Data