Add — Add - Samsung S3F84B8 User Manual

S3F84B8_UM_REV 1.00
6.3.2 ADD — ADD
dst,src
ADD
dst  dst + src
Operation:
The source operand is added to the destination operand. Their sum is stored in the destination.
The contents of source remain unaffected. Two's-complement addition is performed.
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Flags:
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result
is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if a carry from the low-order nibble occurred.
Format:
opc
opc
opc
Given R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, and register 03H = 0AH:
Examples:
ADD
ADD
ADD
ADD
ADD
In the first example, destination working register R1 contains the value 12H and source working
register R2 contains the value 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the
value 15H in register R1.
dst | src
src dst
dst src

R1,R2

R1,@R2

01H,02H

01H,@02H

01H,#25H
Bytes
2
3
3
R1 = 15H, R2 = 03H
R1 = 1CH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 46H
6-14
6 INSTRUCTION SET
Cycles Opcode
(Hex)
4 02
6 03
6 04
6 05
6 06
Addr Mode
dst src
r r
r lr
R R
R IR
R IM