ST STNRG011A User Manual
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ST STNRG011A User Manual

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UM3002
User manual
STNRG011A NVM parameters description
Introduction
This user manual provides information for developing applications with the STNRG011A digital combo multi-mode PFC and
time-shift LLC resonant controller.
®
The STNRG011A is a STMicroelectronics
digital device tailored for SMPS applications. It embodies a multi-mode (transition-
mode and DCM) PFC controller, a high voltage doubleended controller for the LLC resonant half-bridge, an 800 V-rated startup
generator and a sophisticated digital engine, that manages optimal operation of the three blocks.
All the key application parameter of the device are stored into an internal NVM (non-volatile memory), allowing wide
configurability and calibration.
This user manual goes in detail through all the NVM parameters and explains how to set them in a real application. For any
other information about STNRG011A product, please refer to the STNRG011A datasheet.
UM3002 - Rev 1 - April 2022
www.st.com
For further information contact your local STMicroelectronics sales office.

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  • Page 1 UM3002 User manual STNRG011A NVM parameters description Introduction This user manual provides information for developing applications with the STNRG011A digital combo multi-mode PFC and time-shift LLC resonant controller. ® The STNRG011A is a STMicroelectronics digital device tailored for SMPS applications. It embodies a multi-mode (transition- mode and DCM) PFC controller, a high voltage doubleended controller for the LLC resonant half-bridge, an 800 V-rated startup generator and a sophisticated digital engine, that manages optimal operation of the three blocks.

  • Page 2: Notes

    NVM and EEPROM contents checking and programming. For more information about the GUI and the interface board, please refer to the user manual on www.st.com: Getting started with the STEVAL-PCC020V2: USB to I²C UART interface board and associated GUI for STNRG products.

  • Page 3: Equations To Set The Parameters

    UM3002 Equations to set the parameters Equations to set the parameters 2.1.1 PFC power calculation The device uses an internal numerical representation of the power delivered. The relationship between the internal value and the true power is as follows: Equation 1 pinn = P 128 ∙...

  • Page 4: Parameters Description

    • Enabled If patching is disabled the STNRG011A will not upload the patch from the external EEPROM. The default value is disabled (i.e. patching disabled). The user has to maintain the patching feature disabled if no EEPROM is installed on the application.

  • Page 5: Vac Reading Improvement

    UM3002 General system configuration 3.1.5 VAC reading improvement Size:1 bit Enables / disables the VAC reading improvement feature. Available values are: • Disabled • Enabled If the feature is enabled, the IC will sink from the VAC pin I current during line synchronization at VAC_HV_SINK the start-up and I current for about 5 ms in case of the brown-out event, to avoid false brown-in.

  • Page 6: Faults Parameters

    UM3002 Faults parameters Faults parameters 3.2.1 Surge detection Size:1 bit Enable / disable the surge comparator. Available values are: • Disabled • Enabled The surge comparator is connected to the VAC pin and its threshold is 430 V. 3.2.2 PFC OC2 detection Size:1 bit Enables / disables the PFC OC2 comparator.

  • Page 7: Max Number Of Llc Oc2

    UM3002 Faults parameters • Enabled The LLC OC2 comparator is connected to the LLC_CS pin and its threshold is 700 mV. 3.2.6 Max number of LLC OC2 Size: 2 bits Sets the number of consecutive LLC OC2 events before shutting down. Available values are: •...

  • Page 8: Pfc Uvp Behavior

    UM3002 Faults parameters • Not latched • Latched If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults timer” parameter. If the fault is set as “Latched” the switching activity will remain off and the V will remain between 15 V and 17 V using the HV start-up generator (as long as there is the mains connected).

  • Page 9: Llc Olp Behavior

    UM3002 PFC parameters If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults timer” parameter. If the fault is set as “Latched” the switching activity will remain off and the V will remain between 15 V and 17 V using the HV start-up generator (as long as there is the mains connected).

  • Page 10: Pfc Mosfet Leb

    UM3002 PFC parameters • • • Note: The device uses 2 * Kp for calculations (see Section 2.1.2 PFC compensation parameters) 3.3.3 PFC MOSFET LEB Size: 3 bits Sets the PFC MOSFET minimum on-time (also called LEB, i.e. “Leading Edge Blanking”). Available values are: •...

  • Page 11: Pfc Thd Improver Gain

    UM3002 PFC parameters 3.3.5 PFC THD improver gain Size: 3 bits Sets the slope of the ReCOT functionality (THD improver) to compensate for the current in the input capacitors. Available values are: • 0 - gain disabled • • • •...

  • Page 12: Pfc Pss

    Setting the parameter to input power raw value + 30% The value can be further adjusted by looking at the PFC stage transient response. Figure 1. STNRG011A GUI; circled in red the raw value of the input power 3.3.7 PFC pss Size: 3 bits Sets the PFC power during the soft-start.

  • Page 13: Pfc Min Pin Vskip

    UM3002 PFC parameters • 5558 • 7898 • 10238 The higher the value, the higher the maximum on-time of the PFC MOSFET during the burst mode operation. This means that the transferred power will be also higher. The algorithm will adjust the on-time of the PFC MOSFET according to the required power, in order to reduce the acoustic noise.

  • Page 14: Pfc Delta Pin Vskip

    UM3002 PFC parameters • 2048 • 4096 • 2176 • 4224 • 2304 • 4352 • 2432 • 4480 • 2560 • 4608 • 2688 • 4736 • 2816 • 4864 • 2944 • 4992 • 3072 • 5120 • 3200 •...

  • Page 15: Pfc Maximum Dcm Power

    UM3002 PFC parameters 3.3.12 PFC maximum DCM power Size: 4 bits Sets the power threshold to switch from the DCM to the valley-skipping mode. Sets also the on-time duration of the PFC gate drive while in the DCM mode. Available values are: •...

  • Page 16: Pfc Max Tsw Vskip

    UM3002 PFC parameters This value, together with the “PFC Max Tsw Vskip”, is used to set the range of PFC switching frequency; therefore, it is important to optimize the efficiency of the PFC. The max. value should be at least 1.5 times the min. value to avoid the system continuously switching between different modes.

  • Page 17: Pfc Vout Target

    UM3002 PFC parameters Available values are: • • • • • • • • • 1024 • 1280 • 1536 • 1792 • 2048 • 2560 • 3072 • 3584 This parameter can be used to improve efficiency at the power levels at which harmonic contents are not subject to regulation (e.g.

  • Page 18: Pfc Vout Ss End (Delta)

    UM3002 PFC parameters 3.3.17 PFC Vout SS end (delta) Size:2 bits Sets the voltage at which the PFC terminates the soft-start and the system begins the LLC soft-start. Available values are: • 19.5 mV - 3.8 V • 29.3 mV - 5.7 V •...

  • Page 19: Llc Parameters

    “Soft ACP TS decrement”, every time the protection is triggered, for a maximum number of occurrences of “Maximum soft ACP occurrences”. Every time the system triggers the soft ACP feature, the STNRG011A will move to the softstart state, to smoothly recover the regulation.

  • Page 20: Llc Lvg First Ts

    UM3002 LLC parameters At the LLC turn-on, during the safe-start phase, this is the total on-time of the first pulse of the high-side gate drive. Typically, higher values have to be used with high L resonant tanks. 3.4.3 LLC LVG first TS Size: 4 bits Sets the time shift value of the first LLC LVG.

  • Page 21: Minimum Time Shift

    UM3002 LLC parameters The smaller the value the slower will be the output voltage rise and the LLC tank current. The suggestion is to start with the minimum value (usually OK for most applications) and increase it in case a faster Vout rise time is required.

  • Page 22: Maximum Time Shift

    UM3002 LLC parameters Equation 12 f SWmax =   4 ∙ TS min + ZCD delay (12) where TS is the minimum time shift value and ZCD is the delay given by the ZCD comparator and digital delay filtering: ZCD delay = ZCD_comp del + "LLC ZCD comp digital filtering" Equation 13 (13) ZCD_comp...

  • Page 23: Llc Olp Threshold

    This formula can be used to start the design and the value can be fine-tuned at the bench,running the real application prototype. Remember that the STNRG011A provides anti capacitive protection (ACP), so, even if the user puts a large value there is no risk of damaging the board components.

  • Page 24: Llc Olp Timeout

    UM3002 LLC parameters • 373.03 mV • 404.77 mV • 436.52 mV • 468.26 mV • 500 mV The LLC OC1 comparator is used to manage overloads conditions (OLP). This parameter defines the threshold of the current sense level of the application at which the system has to enter the OLP fault, after a timeout defined by the “LLC OLP timeout”.

  • Page 25: Acp Sensitivity

    UM3002 LLC parameters 3.4.12 ACP sensitivity Size: 1 bit Sets the sensitivity on detection ACP condition. Available values are: • • High The ACP sensitivity applies either for hard and soft ACP features. 3.4.13 Hard ACP detection Size: 1 bit Enables / disables the hard ACP detection.

  • Page 26: Maximum Soft Acp Occurrences

    UM3002 Burst mode parameters During the Soft ACP management, the time shift value is decreased by the amount defined by this parameter. This delta is applied immediately, every time the system triggers the soft ACP. The higher the value the faster the shift towards higher switching frequencies.

  • Page 27: Burst Entering Digital Filtering

    UM3002 Burst mode parameters This feature can beuseful in case the resonant tank is not able to regulate the output at light/no loads even at the minimum time shift value. If the time shift has reached its minimum value, the feature allows entering the burst mode if the condition is asserted for at least 480 μs,in addition to the “Burst entering digital filtering”.

  • Page 28: Llc_Fb Burst Wake-Up Thr

    UM3002 Burst mode parameters • 561.5 mV • 1350 ns • 571.3 mV • 1383 ns • 581.1 mV • 1417 ns • 590.8 mV • 1450 ns • 600.6 mV • 1483 ns • 610.4 mV • 1517 ns •...

  • Page 29: Llc_Fb Burst Wake-Up Hyst

    • 3.7 μs During the burst mode, the STNRG011A restarts switching and performs one burst when the LLC_FB pin goes over this threshold. The wake-up threshold on the left has to be set higher than the “LLC_FB burst entering thr”.

  • Page 30: Min Number Of Burst Pulses

    UM3002 Burst mode parameters • 4.07 μs • 4.2 μs • 4.33 μs • 4.47 μs • 4.6 μs • 4.73 μs • 4.87 • 5 μs • 5.13 μs Setting the time shift value (and therefore the switching frequency), is it possible to fix how much energy is transferred to the output by one burst sequence.

  • Page 31: Min Time Between Burst Seq

    UM3002 Burst mode parameters • • • • • • • • • • • • • • • • This parameter defines the maximum number of switching cycles composing a single burst. This condition is reached at medium/high loads (in the burst mode). Please note that this parameter is defined as a positive delta with respect to the “Min number of burst pulses”...

  • Page 32: Minimum Period To Exit Burst

    UM3002 Burst mode parameters During the burst mode, if the load is decreased and the distance between two bursts reaches the value defined by this parameter, the system decreases the number of switching cycles by one. The lower limit for the switching cycles is defined by the “Min number of burst pulses”...

  • Page 33: Comparators Setting

    UM3002 Comparators setting Comparators setting 3.6.1 Surge comp digital filtering Size: 1 bit Sets the digital filtering for the line surge comparator. Available values are: • 100 ns • 500 ns 3.6.2 PFC CS comp digital filtering Size: 2 bits Sets the digital filtering for the PFC CS comparator for the ReCOT functionality (THD improver).

  • Page 34: Pfc Zcd Comp Falling Thr

    UM3002 Comparators setting 3.6.6 PFC ZCD comp falling thr Size: 2 bits Sets the falling threshold for the PFC ZCD comparator (TH_F). Available values are: • 0 mV • 50 mV • 100 mV • 200 mV 3.6.7 PFC ZCD comp rising thr Size: 2 bits Sets the rising threshold for the PFC ZCD comparator (TH_R).

  • Page 35: Llc Zcd Comp Digital Filtering

    UM3002 Comparators setting Available values are: • 133.3 ns • 166.7 ns • 200 ns • 233.3 ns 3.6.11 LLC ZCD comp digital filtering Size: 3 bits Sets the digital filtering for the LLC ZCD comparator. Available values are: • 50 ns •...

  • Page 36: Revision History

    UM3002 Revision history Table 1. Document revision history Date Version Changes 08-Apr-2022 Initial release. UM3002 - Rev 1 page 36/42...

  • Page 37: Table Of Contents

    UM3002 Contents Contents Notes................2 Parameters packing .
  • Page 38 UM3002 Contents PFC parameters ............. . . 9 3.3.1 PFC Ki .
  • Page 39 UM3002 Contents 3.5.1 External burst mode ........... . . 26 3.5.2 BM enter for minimum TS .

  • Page 40: List Of Tables

    UM3002 List of tables List of tables Table 1. Document revision history ............. 36 UM3002 - Rev 1 page 40/42...

  • Page 41: List Of Figures

    STNRG011A GUI; circled in red the raw value of the input power ......
  • Page 42 ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’...

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