Pwm Operation; Prescaler And Divider; Basic Timer Operation - Samsung S5PC110 Manual

S5PC110_UM

1.3 PWM OPERATION

1.3.1 PRESCALER AND DIVIDER

An 8-bit prescaler and 3-bit divider generates the following output frequencies:
Table 1-1 Minimum and Maximum Resolution based on Prescaler and Clock Divider Values
4-bit Divider Settings
1/1( PCLK=66MHz )
1/2 ( PCLK=66MHz )
1/4 ( PCLK=66MHz )
1/8 ( PCLK=66MHz )
1/16 ( PCLK=66MHz )

1.3.2 BASIC TIMER OPERATION

start bit=1 timer is started
TCMPn
TCNTn 3
TCNTBn=3
TCMPBn=1
manual update=1
auto-reload=1
TOUTn
The timer (except the timer channel 4) comprises of four registers, namely, TCNTBn, TCNTn, TCMPBn and
TCMPn. If the timer reaches 0, then TCNTBn and TCMPBn registers are loaded into TCNTn and TCMPn. If
TCNTn reaches 0, then the interrupt request occurs if the interrupt is enabled (TCNTn and TCMPn are the names
of the internal registers. The TCNTn register is read from the TCNTOn register).
Minimum Resolution
(prescaler value=1)
0.030us( 33.0MHz)
0.061us ( 16.5MHz )
0.121us ( 8.25MHz )
0.242us ( 4.13MHz )
0.485us ( 2.06MHz )
TCNTn=TCMPn
1
3 2 1
TCNTBn=2
interrupt request
TCMPBn=0
manual update=0
auto-reload=1
Figure 1-3
1 PULSE WIDTH MODULATION TIMER
Maximum Resolution
(prescaler value=255)
3.879us( 257.8KHz)
7.758us ( 128.9KHz )
15.515us ( 64.5KHz )
31.03us ( 32.2KHz )
62.061us ( 16.1KHz )
auto-reload
TCNTn=TCMPn
0
0 2 1
auto-reload=0
interrupt request
Timer Operations
Maximum Interval
(TCNTBn=4294967295)
16659.27s
33318.53s
66637.07s
133274.14s
266548.27s
timer is stopped.
0 0
command
status
1-5