Samsung S5PC110 Manual page 820

S5PC110_UM
1.6.1.3 UART FIFO Control Register
•
UFCON0, R/W, Address = 0xE290_0008
•
UFCON1, R/W, Address = 0xE290_0408
•
UFCON2, R/W, Address = 0xE290_0808
•
UFCON3, R/W, Address = 0xE290_0C08
There are four UART FIFO control registers in the UART block, namely, UFCON0, UFCON1, UFCON2 and
UFCON3.
UFCONn Bit
Reserved [31:11]
Tx FIFO Trigger [10:8]
Level
Reserved
Rx FIFO Trigger [6:4]
Level
Reserved
Determines the trigger level of Tx FIFO. If data count of Tx FIFO is
less than or equal to the trigger level, Tx interrupt occurs.
[Channel 0]
000 = 0 byte
010 = 64 bytes
100 = 128 bytes
110 = 192 bytes
[Channel 1]
000 = 0 byte
010 = 16 bytes
100 = 32 bytes
110 = 48 bytes
[Channel 2, 3]
000 = 0 byte
010 = 4 bytes
100 = 8 bytes
110 = 12 bytes
[7] Reserved
Determines the trigger level of Rx FIFO. If data count of Rx FIFO
is more than or equal to the trigger level, Rx interrupt occurs.
[Channel 0]
000 = 32 byte
010 = 96 bytes
100 = 160 bytes
110 = 224 bytes
[Channel 1]
000 = 8 byte
010 = 24 bytes
100 = 40 bytes
110 = 56 bytes
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
Description
001 = 32 bytes
011 = 96 bytes
101 = 160 bytes
111 = 224 bytes
001 = 8 bytes
011 = 24 bytes
101 = 40 bytes
111 = 56 bytes
001 = 2 bytes
011 = 6 bytes
101 = 10 bytes
111 = 14 bytes
001 = 64 bytes
011 = 128 bytes
101 = 192 bytes
111 = 256 bytes
001 = 16 bytes
011 = 32 bytes
101 = 48 bytes
111 = 64 bytes
Initial State
0
000
0
000
1-18