Table 4-5. Identifying Sdram Bank In Error - Motorola MVME1X7P Programmer's Reference Manual

Since the memory architecture is 32 data bits plus seven syndrome bits
with a non-interleaved architecture, there is no corresponding entry for
Bank in Error. The selection of the physical SDRAM bank is decoded from
the address bus. Consequently, the Error Address register must be
examined to determine which bank contains the error. Given a specific
SDRAM configuration, the following table relates bits in the Error
Address register to the physical bank where the error originated.
.

Table 4-5. Identifying SDRAM Bank in Error

SDCFG2
0
0
0
0
1
1
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SDCFG1 SDCFG0
0 0 Device is 64Mbit x 16 data with one
bank composed of 3 devices.
0 1 Device is 64Mbit x 8 data with one
bank composed of 5 devices.
1 0 Device is 64Mbit x 8 data with two
banks composed of 5 devices each.
If EA24 = 0, Bank 0
If EA24 = 1, Bank 1
1 1 Device is 64Mbit x 8 data with four
banks composed of 5 devices each.
If EA[25:24] = 00, Bank 0
If EA[25:24] = 01, Bank 1
If EA[25:24] = 10, Bank 2
If EA[25:24] = 11,Bank 3
0 0 Device is 128Mbit x 8 data with one
bank composed of 5 devices.
0 1 Device is 128Mbit x 8 data with two
banks composed of 5 devices each.
If EA25 = 0, Bank 0
If EA25 = 1, Bank 1
DRAM Array Size and Bank with
the Error
Syndrome Decoding
4-37
4