Interrupt Level Register 4 (Bits 0-7); Vector Base Register - Motorola MVME1X7P Programmer's Reference Manual

Interrupt Level Register 4 (bits 0-7)

ADR/SIZ
BIT
7
NAME
OPER
RESET
This register is used to define the level of the VMEbus level 1 (IRQ1)
interrupt and the VMEbus level 2 (IRQ2) interrupt. The IRQ1 and IRQ2
interrupts may be mapped to any local bus interrupt level.
VIRQ1 LEVEL
VIRQ2 LEVEL

Vector Base Register

ADR/SIZ
BIT 31
NAME
OPER
RESET
This register is used to define the interrupt base vectors.
VBR 1
VBR 0
Note
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$FFF40084 (8 bits [6 used] of 32)
6 5
VIRQ2
R/W
0 PSL
These bits define the level of the VMEbus IRQ1 interrupt.
These bits define the level of the VMEbus IRQ2 interrupt.
$FFF40088 (8 bits of 32)
30 29 28
VBR 0
R/W
0 PSL
These bits define the interrupt base vector 1.
These bits define the interrupt base vector 0.
Refer to Table 2-4, Local Bus Interrupter Summary, for
further information.
A suggested setting for the VMEchip2 Vector Base register
is: VBR0 = 6, VBR1 = 7 (i.e., setting the Vector Base register
at address $FFF40088 to $67xxxxxx). This produces a
Vector Base0 of $60 corresponding to the "X" in
and a Vector Base1 of $70 corresponding to the "Y" in
2-4.
LCSR Programming Model
4 3 2
VIRQ1 LEVEL
27 26
VBR 1
R/W
0 PSL
1 0
R/W
0 PSL
25 24
Table 2-4,
Table
2-95
2