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ECC
The Petra MCECC sector pair performs single-bit error correction and
double-bit error detection (SECDED). Since the SDRAM device can
deliver data from incremental addresses with each clock tick (subject to
boundary limitations), the Petra MCECC sector does not implement an
interleaved memory architecture. The SDRAM array is 32 data bits plus
seven checkbits wide. The depth is dependent on the number and type of
SDRAM devices.
Cycle Types
The Petra MCECC sector always initiates burst read/write accesses to the
SDRAM device. If the bus access is not a burst, the cycle is terminated
early. Single- and double-byte write cycles are read-modify-write
accesses, but longword write accesses require no read cycle.
Error Reporting
The Petra MCECC sector generates ECC check bits for write cycles. It also
checks read data from the DRAM and corrects the data if it contains a
single-bit error. If a non-correctable error occurs within the read data, the
Petra MCECC sector so indicates by asserting its non-correctable error
(NCE ) pin.
The following paragraphs describe the actions that the MCECC sector will
take in different error situations.
Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)
1. Correct the data that is driven to the local MC680x0 bus.
2. Do not correct the data in DRAM. The DRAM is not corrected until
3. Terminate the cycle normally. (Assert TA to the local bus.)
4. Log the error if not already logged.
5. Notify the local MPU via interrupt, if so enabled.
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the next scrub of that address, which happens only if scrubbing is
enabled.
Functional Description
4-5
4
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