Watchdog Timer Control Register - Motorola MVME1X7P Programmer's Reference Manual

Single-board computer
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Watchdog Timer Control Register

ADR/SIZ
BIT
23
NAME
SRST
OPER
S
RESET
0 PS
WDEN
WDRSE
WDS/L
WDBFE
WDTO
WDCC
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$FFF40060 (8 bits of 32)
22
21
20
WDCS
WDCC
WDTO WDBFE WDS/L WDRSE WDEN
C
C
R
0
0
0 P
When this bit is high, the watchdog timer is enabled.
When this bit is low, the watchdog timer is not enabled.
When this bit is high, and a watchdog time-out occurs, a
SYSRESET or LRESET is generated. The WDS/L bit in
this register selects the reset. When this bit is low, a
watchdog time-out does not cause a reset.
When this bit is high and the watchdog timer has timed
out and the watchdog reset enable (WDRSE bit in this
register) is high, a SYSRESET signal is generated on the
VMEbus which in turn causes LRESET to be asserted.
When this bit is low and the watchdog timer has timed out
and the watchdog reset enable (WDRSE bit in this
register) is high, an LRESET signal is generated on the
local bus.
When this bit is high and the watchdog timer has timed
out, the VMEchip2 asserts the BRDFAIL signal pin.
When this bit is low, the watchdog timer does not
contribute to the BRDFAIL signal on the VMEchip2.
When this status bit is high, a watchdog time-out has
occurred. When this status bit is low, a watchdog time-out
has not occurred. This bit is cleared by writing a 1 to the
WDCS bit in this register.
When this bit is set high, the watchdog counter is reset.
The counter must be reset within the time-out period or a
watchdog time-out occurs.
LCSR Programming Model
19
18
17
R/W
R/W
R/W
0 PSL
0 PSL
1 PSL
2
16
R/W
0 PSL
2-71

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