Vmebus Interrupter Control Register - Motorola MVME1X7P Programmer's Reference Manual

VMEbus Interrupter Control Register

ADR/SIZ
BIT
31
NAME
OPER
RESET
This register controls the VMEbus interrupter.
IRQL
IRQS
IRQC
IRQ1S
http://www.motorola.com/computer/literature
$FFF40048 (8 bits [7 used] of 32)
30 29 28
IRQ1S IRQC
R/W S
0 PS 0 PS
These bits define the level of the VMEbus interrupt
generated by the VMEchip2. A VMEbus interrupt is
generated by writing the desired level to these bits. These
bits always read 0 and writing 0 to these bits has no effect.
This bit is the IRQ status bit. When this bit is high, the
VMEbus interrupt has not been acknowledged. When this
bit is low, the VMEbus interrupt has been acknowledged.
This is a read-only status bit.
This bit is the VMEbus interrupt clear bit. When this bit is
set high, the VMEbus interrupt is removed. This feature is
only used when the IRQ1 broadcast mode is used. Normal
VMEbus interrupts should never be cleared. This bit
always reads 0; writing a 0 to it has no effect.
These bits control the function of the IRQ1 signal line on
the VMEbus:
0 The IRQ1 signal from the interrupter is
connected to the VMEbus IRQ1 signal line.
1 The output from tick timer 1 is connected to
the VMEbus IRQ1 signal line.
2 The IRQ1 signal from the interrupter is
connected to the VMEbus IRQ1 signal line.
3 The output from tick timer 2 is connected to
the VMEbus IRQ1 signal line.
LCSR Programming Model
27 26 25
IRQS IRQL
R S
0 PS 0 PS
2
24
2-61