Interrupt Mask Level Register - Motorola MVME1X7P Programmer's Reference Manual

Interrupt Mask Level Register

ADR/SIZ
BIT
7
NAME
OPER
R
RESET
0
MSK2-MSK0 Interrupt Mask Level - The interrupt mask level bits
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$FFF4203F (8 bits)
6 5 4
R R R
0 0 0
determine the level which must be exceeded by IPL2-
IPL0 in order for the PCCchip2 to assert its INT pin. The
MSK bits are encoded as follows:
MSK2 MSK1 MSK0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Programming Model
3 2
MSK2 MSK1
R R/W
0 1 PL
Priority Level
0 0
1 1
0 2
1 3
0 4
1 5
0 6
1 7
1 0
MSK0
R/W R/W
1 PL 1 PL
Comments
Lowest Level
Highest Level
3-49
3