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Arbitration
The MCECC sector has three different entities that can request use of the
DRAM cycle controller: (1) the local bus master, (2) the refresher, and (3)
the scrubber.
The MCECC pair arbiter accepts requests and provides grants to the
requesting entities as follows:
Chip Defaults
Certain parameters in the Petra MCECC sector have to be configured.
These include DRAM size, DRAM speed, Control and Status register
selection, etc. The configuration parameters are loaded into the Defaults
1, Defaults 2, and SDRAM Configuration registers on the first clock edge
after reset negation. Software can override this initial setting by writing to
the Defaults registers. However, it is not recommended that non-test
software alter the contents of the Defaults registers. The actual values
loaded into the Defaults registers are determined by board-level jumpers
and configuration resistors.
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Priority is (highest to lowest) refresher, local bus, and scrubber.
When no requests are pending, the arbiter defaults to providing a
local bus grant for fast response to local bus cycles.
Although the arbiter operates on a priority basis, it also performs a
pseudo round robin algorithm in order to prevent starving any of the
requesting entities.
Functional Description
4-9
4
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