Table of Contents
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B
Back Off signal (PCCchip2 ASIC)
backward compatibility
base address, VMEchip2 LCSR
battery backup
BBRAM
configuration area memory map
interface, PCCchip2
memory map
speed control
BBRAM (battery-backed-up RAM)
restoring lost Ethernet address
BBSY* signal, VMEbus
BERR* signal, VMEbus
BGIN filters, VMEbus
binary number, symbol for
block (D64) access cycles, VMEbus 2-33,
2-36
block access cycles, VMEbus 2-33,
block diagrams
MVME1X7P board
PCCchip2 ASIC
VMEchip2 ASIC
block transfer
cycles, VMEchip2 DMAC
mode
2-9
modes, DMAC
board
address, GCSR
failure signal, VMEchip2 ASIC
ID
1-44
serial number
speed
1-46
status/control register, VMEchip2
Board Control register, VMEchip2
I
BRDFAIL* signal pin, VMEchip2 ASIC
N
2-70,
D
broadcast interrupt function (VMEchip2
E
timers)
broadcast mode, VMEbus
X
BSY signal and arbitration timer
burst read cycle type
IN-2
3-5
1-2
2-20
1-10
1-42
3-3
1-41
3-15
1-12
1-15
2-98
2-17
2-98
xxiii
2-36
1-4
3-2
2-5
2-11
2-59
2-48
2-70
1-44
2-101
2-71
2-15
2-16
2-17
4-5
burst write cycle type
bus error
3-4
processing
sources
1-54
status, SCSI
bus map decoder, LCSR
bus sizing, VMEchip2 ASIC
bus timer (local)
bus timer enable/disable, VMEbus
bus timers, example of use
byte counter, DMAC
C
cache coherency
MCECC sector
MVME1x7P
cache inhibit function
cautions for use of reset (VMEchip2)
CD2401 serial controller chip 1-12,
memory map
changes from previous boards
checksum byte
chip arbiter, VMEbus
chip ID and revision registers (VMEchip2
ASIC)
Chip ID register
MCECC sector
PCCchip2 ASIC
Chip Revision register
MCECC sector
PCCchip2 ASIC
Chip Speed register (PCCchip2 ASIC)
clear bits
LANC error
2-106
SCSI error
clear overflow counter
tick timer 1
tick timer 2
clear-on-compare
tick timer 1
tick timer 2
Computer Group Literature Center Web Site
Index
4-6
1-55
3-37
2-20
2-6
1-17
2-17
1-51
2-60
4-4
1-49
1-20
2-101
3-7
1-36
A-1
1-46
2-17
2-100
4-13
3-14
4-13
3-14
3-46
3-34
3-37
3-23
3-22
3-23
3-22
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