Table of Contents
Advertisement
PCCchip2
Printer PE Interrupt Control Register
ADR/SIZ
BIT
3
NAME
OPER
RESET
3-42
7
6
PLTY
E/L*
INT
R/W
R/W
0 PL
0 PL
0 PL
IL2-IL0
These three bits select the interrupt level for the printer
PE. Level 0 does not generate an interrupt.
ICLR
In edge-sensitive mode, writing a logic 1 to this bit clears
the INT status bit. This bit has no function in level-
sensitive mode. This bit is always read as zero.
IEN
When this bit is high, the interrupt is enabled. The
interrupt is disabled when this bit is low.
INT
When this bit is high, a printer PE interrupt is being
generated at the level programmed in IL2-IL0 (if
nonzero).
E/L*
When this bit is high, the interrupt is edge-sensitive. The
interrupt is level-sensitive when this bit is low.
PLTY
When this bit is low, interrupt is activated by a rising
edge/high level of the PE pin.
When this bit is high, interrupt is activated by a falling
edge/low level of the PE pin.
Note that if this bit is changed while the E/L* bit is set (or
is being set), a PE interrupt may be generated. This can be
avoided by setting the ICLR bit during write cycles that
change the E/L* bit.
$FFF42033 (8 bits)
5
4
3
IEN
ICLR
R
R/W
C
0 PL
0 PL
Computer Group Literature Center Web Site
2
1
0
IL2
IL1
IL0
R/W
R/W
R/W
0 PL
0 PL
0 PL
Advertisement
Table of Contents
