General Purpose Input/Output Pin Control Register; Tick Timer 2 Interrupt Control Register - Motorola MVME1X7P Programmer's Reference Manual

General Purpose Input/Output Pin Control Register

ADR/SIZ
BIT
23
NAME
OPER
R
RESET
0
GPO
GPOE
GPI

Tick Timer 2 Interrupt Control Register

ADR/SIZ
BIT 15
NAME
OPER R
RESET
0
IL2-IL0
ICLR
IEN
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$FFF42019 (8 bits)
22 21 20
R R R
0 0 0
When GPO is set, and GPOE is set, the GPIO pin is at a
logic high level. When GPO is cleared, and GPOE is set,
the GPIO pin is at a logic low level.
This bit controls whether or not the PCCchip2 drives the
GPIO pin. When GPOE is set, the PCCchip2 drives the
GPIO pin. When GPOE is cleared, the PCCchip2 does not
drive the GPIO pin.
This bit reflects the state of the GPIO pin. It is set when
GPIO is high and cleared when GPIO is low. On the
Single-Board Computers, the PCCGPIO1 pin is
connected to the remote reset connector pin 19.
$FFF4201A (8 bits)
14 13 12
INT IEN
R R R/W
0 0 PL 0 PL
Interrupt Request Level. These three bits select the
interrupt level for Tick Timer 2. Level 0 does not generate
an interrupt.
Writing a logic 1 into this bit clears the INT status bit.
This bit is always read as zero.
Interrupt Enable. When this bit is high, the interrupt is
enabled. The interrupt is disabled when this bit is low.
Programming Model
19 18 17
GPI GPOE
R R R/W
0 X 0 PL
11 10 9
ICLR IL2 IL1
C R/W R/W
0 PL 0 PL 0 PL
16
3
GPO
R/W
0 PL
8
IL0
R/W
0 PL
3-25