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VMEchip2
I/O Control Register 1
2
ADR/SIZ
BIT
NAME
OPER
RESET
2-96
23
22
21
MIEN
SYSFL
ACFL
R/W
R
0 PSL
X
This register is a general purpose I/O control register. Bits 16-19 control
the direction of the four General Purpose I/O pins (GPIO0-3).
GPOEN0
When this bit is low, the GPIO0 pin is an input.
When this bit is high, the GPIO0 pin is an output.
GPOEN1
When this bit is low, the GPIO1 pin is an input.
When this bit is high, the GPIO1 pin is an output.
GPOEN2
When this bit is low, the GPIO2 pin is an input.
When this bit is high, the GPIO2 pin is an output.
GPOEN3
When this bit is low, the GPIO3 pin is an input.
When this bit is high, the GPIO3 pin is an output.
ABRTL
This bit indicates the status of the
When this bit is high, the
When this bit is low, the
ACFL
This bit indicates the status of the ACFAIL signal line on
the VMEbus. When this bit is high, the ACFAIL signal
line is active. When this bit is low, the ACFAIL signal line
is not active.
SYSFL
This bit indicates the status of the SYSFAIL signal line on
the VMEbus. When this bit is high, the SYSFAIL signal
line is active. When this bit is low, the SYSFAIL signal
line is not active.
MIEN
When this bit is low, all interrupts controlled by the
VMEchip2 are masked. When this bit is high, all
interrupts controlled by the VMEchip2 are not masked.
$FFF40088 (8 bits of 32)
20
19
ABRTL
GPOEN3 GPOEN2 GPOEN1 GPOEN0
R
R
R/W
X
X
0 PS
ABORT
ABORT
Computer Group Literature Center Web Site
18
17
16
R/W
R/W
R/W
0 PS
0 PS
0 PS
switch.
ABORT
switch is depressed.
switch is not depressed.
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